Administrivia Joe s lab hours Monday 6 8 Tuesday 6 9 Thursday 6 9 Any problems with lab 1 Fetch Unit CSE141L Lab 1b The Instruction Execution Cycle Obtain instruction from program storage Instruction Fetch Determine required actions and instruction size Instruction Decode Locate and obtain operand data Operand Fetch Compute result value or status Execute Result Store Next Instruction 3 Deposit results in storage for later use Determine successor instruction Fetch Unit Fetch instructions from I mem Supply instructions to the Exec Unit Why use a FIFO Fetch Unit fetch FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO deque instruction addr Exec Unit BackEnd Fetch Unit Roles Supply instructions to the exec unit Service I Mem operations load an instruction store an instruction Branch Prediction if cond do A else do B fetch A or B Instead of waiting the result of condition evaluation predict where to go For a misprediction a recovery mechanism required Simple Static Branch Prediction Opcode P Offset P 1bit prediction bit 0 not a branch or a branch predicted untaken 1 a branch and predicted taken Branch target address PC 9 0 PC 10bits Offset 5bits Offset 4 0 ADD Sign Offset 9 0 Extend Fetch Unit Interface deque Instruction data addr valid restart restart addr Fetch Unit Exec Unit memory req load store addr store data load data load valid module fetch parameter I WIDTH 17 A WIDTH 10 O WIDTH 5 input clk reset normal operation signals from the backend end input deque input restart input A WIDTH 1 0 restart addr normal operation signals from the front end to backend output I WIDTH 1 0 instruction data output A WIDTH 1 0 instruction addr output instruction valid input A WIDTH 1 0 load store addr input I WIDTH 1 0 store data output I WIDTH 1 0 load data output load valid input load store 1 0 input do load store Fetch Unit Operations deque simple fetch restart memory load store Operation Fetch If reset Fetch the instruction at 0x0 Else If branch branch predicted Fetch the instruction at the branch target address Else Fetch the instruction at PC 1 Operation Restart Why Restart Operations discard all the instructions in FIFO Fetch the instruction at restart addr Priority Reset Restart Normal Fetch Operation Memory Memory Operations Load read a data from the specified addr of the I Mem Store write a data to the specified addr of the I Mem At most only one operation can be performed in a cycle Priority why 1 load store 2 reset 3 restart 4 normal fetch Control sel pc sel addr fifo enque ram we pc 9 0 din 26 17 instruction addr 9 0 0x0 pc prev r 9 0 instruction data 16 0 1 FIFO pc 9 0 Offset restart addr 9 0 din 16 0 ram addr 9 0 restart addr r 9 0 deque loadstore addr 9 0 SRAM loadstore addr r 9 0 store data 16 0 load data 16 0 store data r 16 0 ram data 4 0 Datapath Lab 2 Due next Friday Goal Make the datapath Work Understand the given datapath Use given 2 module RAM FIFO Implement 2 modules Adder Sign extender Connect all things together Synthesize Implement and analyze Detailed instructions will be available tonight
View Full Document
Unlocking...