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UCSD CSE 141L - Fetch Unit

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Administrivia • Joe’s lab hours – Monday 6-8, Tuesday 6-9, Thursday 6-9 • Any problems with lab 1?Fetch Unit CSE141L Lab 1b3 The Instruction Execution Cycle Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine successor instruction Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next InstructionFetch Unit? • Fetch instructions from I-mem • Supply instructions to the Exec Unit • Why use a FIFO? Fetch Unit FIFO fetch instruction addr deque FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO Exec Unit (“BackEnd”)Fetch Unit Roles • Supply instructions to the exec unit • Service I-Mem operations – load an instruction – store an instruction • Branch Prediction – if (cond) do A, else do B • fetch A or B? – Instead of waiting the result of condition evaluation, predict where to go – For a misprediction, a recovery mechanism requiredSimple Static Branch Prediction • P(1bit) - prediction bit – 0: not a branch, or a branch predicted untaken – 1: a branch, and predicted taken • Branch target address – PC(10bits) + Offset(5bits) P Opcode Offset Sign Extend ADD PC [9:0] Offset [4:0] Offset [9:0]Fetch Unit Interface Fetch Unit Instruction(data, addr, valid) deque restart restart_addr memory req (load, store, addr, store_data) load_data, load_valid Exec Unitmodule fetch #(parameter I_WIDTH = 17, A_WIDTH = 10, O_WIDTH= 5) ( input clk, reset, // normal operation, signals from the backend end input deque, input restart, input [A_WIDTH-1:0] restart_addr, // normal operation, signals from the front end to backend output [I_WIDTH-1:0] instruction_data, output [A_WIDTH-1:0] instruction_addr, output instruction_valid, input [A_WIDTH-1:0] load_store_addr, input [I_WIDTH-1:0] store_data, output [I_WIDTH-1:0] load_data, output load_valid, input load_store_1_0; input do_load_store; )Fetch Unit Operations • deque – simple • fetch • restart • memory – load – storeOperation - Fetch • If reset – Fetch the instruction at 0x0 • Else If (branch | branch_predicted) – Fetch the instruction at the branch target address • Else – Fetch the instruction at {PC + 1}Operation - Restart • Why Restart? • Operations – discard all the instructions in FIFO – Fetch the instruction at restart_addr • Priority? – Reset > Restart > Normal FetchOperation - Memory • Memory Operations – Load: read a data from the specified addr of the I-Mem – Store: write a data to the specified addr of the I-Mem – At most only one operation can be performed in a cycle • Priority: why? – 1. load = store – 2. reset – 3. restart – 4. normal fetchSRAM FIFO +1 +Offset 0x0 pc [9:0] pc_prev_r[9:0] restart_addr_r [9:0] loadstore_addr_r [9:0] store_data_r [16:0] din[26:17] din[16:0] load_data[16:0] instruction_addr[9:0] instruction_data[16:0] pc[9:0] deque ram_addr[9:0] ram_we sel_addr sel_pc fifo_enque restart_addr [9:0] loadstore_addr [9:0] store_data [16:0] Control Datapath ram_data [4:0]Lab 2 • Due next Friday • Goal – Make the datapath Work • Understand the given datapath • Use given 2 module – RAM – FIFO • Implement 2 modules – Adder – Sign extender • Connect all things together • Synthesize, Implement, and analyze • …… • Detailed instructions will be available


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