Slide 1Slide 2Slide 3Slide 4State Machines Tutorial CSE 141 LFinite State Machines (FSMs)●Useful for designing many different types of circuits●3 basic components:–Combinational logic (next state)– Sequential logic (store state)–Output logic●Different encodings for state:–Binary (min FF’s), Gray, One hot (good for FPGA), One cold, etcA simple FSM in Verilogmodule simple_fsm( input clk, start,output restart);reg [1:0] state, next_state;parameter S0 = 2’b00, S1 = 2’b01, S2 = 2’b10; // binary encodealways @ (*)begin : next_state_logiccase ( state )S0: begin if ( start ) next_state = S1; else next_state = S0; endS1: begin next_state = S2; endS2: begin if (restart) next_state = S0; else next_state = S2; enddefault: next_state = S0;endcaseend // continued to the right// continued from leftalways @ (posedge clk)begin: state_assignment state <= next_state;endendmoduleTips on FSMs● Don’t forget to handle the default case● Use two different always blocks for next state and state assignment●Can do it in one big block but not as clear● Outputs can be a mix of combin. and seq.●Moore Machine: Output only depends on state●Mealy Machine: Output depends on state and
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