State Machines Tutorial CSE 141 L Finite State Machines FSMs Useful for designing many different types of circuits 3 basic components Combinational logic next state Sequential logic store state Output logic Different encodings for state Binary min FF s Gray One hot good for FPGA One cold etc A simple FSM in Verilog module simple fsm input clk start output restart reg 1 0 state next state parameter S0 2 b00 S1 2 b01 S2 2 b10 binary encode always begin next state logic case state S0 begin if start next state S1 else next state S0 end S1 begin next state S2 end S2 begin continued from left if restart next state S0 always posedge clk else next state S2 begin state assignment end state next state default next state S0 endcase end end continued to the right endmodule Tips on FSMs Don t forget to handle the default case Use two different always blocks for next state and state assignment Can do it in one big block but not as clear Outputs can be a mix of combin and seq Moore Machine Output only depends on state Mealy Machine Output depends on state and inputs
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