CSE 141L Steven Swanson Vikram Bhatt Meenakshi Sundaram 1 You will design and implement a microprocessor this quarter 2 Course Goals what you learned in 141 Apply architecture play itself out in a real design See more Verilog Learn experience working on a large scale project Get Have Fun hear I forget I see I remember I do I Iunderstand 3 Course Format labs SixMore about these in a moment Lectures Verilog coding Discuss current or upcoming lab Work through part of the lab Answer questions about the lab Sort of like group office hours 4 Lab 1 Introduction Xilinx ISE week 1Two Xilinx tutorials Building projects Entering verilog Simulation etc simulate and synthesize simple circuits Build their properties Measure are skills you will need throughout the These class Start now 5 Lab 2 Simple Datapath week 1Implement processor the datapath for a brain dead 16 bit instruction 8 bit data 9 instructions Add Sub Mult Ld St Li Read Write Halt TrivialScalar op code regfile write en reg sel dmem write en read write req 1 r1 r2 PC Imem Decode 0 inst run stall reset TrivialScalar Control Lab 3 next pc Reg File imm v1 ALU r data v2 Dmem ld data result st data addr 6 Lab 3 Simple Control week 1Add control the datapath in Lab 2 Execute simple programs have now built a simple processor You a very useful one But not 7 Lab 4 Your own datapath 2Useweeks an ISA from cse141 Design and the implement the datapath needed to execute the instructions Design review with another team 8 Lab 5 Control for your processor weeks 2Implement control path for your processor You will nowthehave a working CPU Hurrah Evaluate the performance some simple benchmarks of your CPU with 9 Lab 6 Make your CPU Cooler weeks 2 3 sky is the limit ThePipelining Build a multiprocessor Branch prediction Speculation Multi media instructions 10 Link to 141 do not need to be in 141 to take 141L You will use the results of the 141 project in this We class 141 Project Design a 17 bit instruction 34 bit data ISA Due just before the start of Lab 3 License is free to you The licenser gets extra credit you are not in 141 you will license an ISA Iffrom one of the groups in 141 11 Doing the work will be done independently Lab1 2 6 will be in groups of 2 3 LabHigher standards for groups of 3 Regrouping is allowed for labs 4 6 Choose your groups carefully If your group breaks up at after lab 4 begins you are stuck philosophy is learn by doing TheYouoverarching and your group must do all your own coding and design You should absolutely talk to other students in the class about Xilinx problems design options etc Labs 1 3 are specifically for this you are all building the same thing Learn from each other 12 Lab space and Software will use the Xilinx tools for development WeVerilog entry Simulation Debugging facilities Like all hardware design tools there are bugs These are among the best tools available hard as that may be to believe labs in the CSE basement have the tools The installed B230 and B240 only are also available for free see link on the They website MUST GET VERSION 11 5 AND INSTALL YOU ALL THE PATCHES The current version is 12 We are not using 12 13 Course Staff Steven Swanson Prof TAs Vikram Bhatt Meenakshi Sundara of us will be in the lab One 2 3 nights per week We hate to be lonely ebu3b B230 and B240 course web site for See details 14 Grading grading schemes Two BySixthelabsnumbers class participation Equal weight on each 14 per lab 16 participation Outcome based Do a reasonable job on the labs at least a C Deliver a working processor You get an A 15