1CSE 141LComputer Architecture LabSummer Session I, 2005Lecture 3Pramod V. ArgadeJuly 12th, 2005Slide 3-2Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005CSE141: Computer Architecture LabInstructor: Pramod V. Argade ([email protected])Office Hour: Tue. 7:30 - 8:50 PM (Center 105)Wed. 5:00 - 6:00 PM (HSS 1330)And, by appointment.TAs :Anjum Gupta: [email protected] Jianhua Liu: [email protected]:Anthony Choi: [email protected] Chin: [email protected]:LogicWorks 5, Interactive Circuit Design SoftwareCapilano Computing Systems, 2004 (Available in UCSD Bookstore.)Web-page: http://www.cse.ucsd.edu/classes/su05/cse141L2Slide 3-3Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005CSE141L Course ScheduleLecture # Date Time Room TopicAssignmentDue1 Tue. 6/28 6 - 7:15 PM Center 105 Assignment 1: ISA -2 Tue. 7/5 6 - 7:15 PM Center 105Assignment 2:Assembler & ISS#13 Tue. 7/12 6 - 7:15 PM Center 105 Assignment 3: Datapath #24 Tue. 7/19 6 - 7:15 PM Center 105 Assignment 4: CPU #3- Tue. 7/26July 26 - 28: Students demonstrate their working CPU Design to TAs by appointment.Assignment #4 reports are due July 26th at 6 PM in the Lab (AP&M 2444?).No LectureSlide 3-4Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005Microprocessor Design StepsüDesign Instruction Set Architecture (ISA)üCode applicationsüDevelop software generation tools üDevelop instruction set simulator (ISS)•Design datapath, verify it•Design the Processor, simulate logic•Verify the processor•Fabricate the chip3Slide 3-5Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005Processor: A State Machine!Flipflop(s)CombinationalLogicSlide 3-6Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005What is a data path?•Path along which data in a processor passes•Data path consists of–Internal storage•General purpose register file•Special registers–ALU–Some control logic•e.g. signals to control ALU operation4Slide 3-7Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005Example Instruction Formats$DOPCExample 1: ADD InstructionADD RD, $ConstantRD= RD+ $ConstantExample 2: MOV InstructionMOV RD, RSRD= RSSDOPCSlide 3-8Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005Processor OrganizationI-MemRegister FileCPU ControlLogicPCALUD-MemCLKSRCDSTOPC2:1 MultiplexorCLKALUControlLogicInstruction-OPCODEALU-OPNote: Blocks in your architecture equivalent to those in green are to be implemented in Lab32:1 Multiplexor5Slide 3-9Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005Lab 3 Assignment•Design data path for your 8-bit processor architecture•Use LogicWorks 5 to design the data path•Simulate the data path Slide 3-10Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005What you must include•All internal storage in your architecture. – General purpose register file– Stack– Accumulator– Special registers, status flag(s), etc.•Arithmetic Logical Unit– Implement data path for all instructions that manipulate data in some way•MOV, both immediate-to-register and register-to-register•ADD, SUB, XOR, SHIFT, …•Interconnections between modules•Logic to control components of ALU6Slide 3-11Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005What you don’t have to implement•Following instructions•Control transfer instructions (branches, jumps, etc.)•Memory load/store instructions•Program Counter (PC)•I-Mem•D-MemSlide 3-12Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005How you should test data path• Stimulus generation: – Binary switches– Hex keypads• Mechanisms to observe results: – Binary displays– Hex displays• Internal variables on the timing diagrams7Slide 3-13Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005Slide 3-14Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005What you will turn in for this Lab• Summary of your ISA from Lab 1.• Printed schematics for the top level data path you designed in LogicWorks 5. No need to submit all the lower level schematics• Printout of waveforms that show example input data, ALU opcode and the result from the ALU for each instruction.• All the LogicWorks 5 files you created (to be submitted using turnin script).• Description of the procedure to follow in order to test the operation of the data path for each instruction for your processor. This is so your TA can test your design.• Answers to following questions.8Slide 3-15Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005Questions• Which instruction is the most expensive in terms of number of gates it requires (no need to give the exact gate count, just give the reasoning).• What tricks did you use to decrease the logic in your data path by sharing the logic among more than one instruction?• How does your "move constant to register" and "move register to register" instruction work? Is it a special case of another ALU instruction, or does it use special data path elements?• Using your data path, explain how you will load a register with a value from a memory location and store contents of a register to a memory location.Slide 3-16Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005You should show on waveforms and Demo to TA• Ability to load a constant with the required number of bits for your ISA into any appropriate register (e.g. any general purpose register).• Correct operation of the ALU for all the ALU opcodessupported.• Ability to have the same register to be the source and destination of an instruction.• Show the ALU operation for interesting input data. For example, if the carry from the adder is saved in your architecture, use data that both does and does not set the carry bit.9Slide 3-17Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005Working knowledge of LogicWorks 5 Assumed!• Various components available in Standard Libraries, such as, D Flip-flop, logic gates, multiplexors, registers, adders, clock, binary switch, binary display, hex keypad, hex display, etc.• How to connect a bus to various components.• How to define a sub-circuit bottom up, i.e. create a circuit and then use it to define the pins on the parent symbol.• How to simulate a circuit and generate waveforms.• How to print a circuit and waveforms.Slide 3-18Pramod ArgadeUCSD CSE 141L, Summer Session 2, 2005Useful Hints•Build hierarchical design•Test thoroughly at every level of hierarchy–Connect binary switches and hex keypads to provide inputs–Connect binary and hex displays to observe behavior–Test combinations of control signals–Test all corner cases for