Courtesy of Arvind http://csg.csail.mit.edu/6.375/ L02-1 Verilog 1 - Fundamentals 6.375 Complex Digital Systems Arvind FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); endmoduleWhat is Verilog? ! Verilog is a hardware description language  There is more to it than that, but this is what we will use it for. ! In this class, Verilog is an implementation language, not a design language  When you sit down to write verilog you should know exactly what you are implementing.  Draw your schematic and state machines and transcribe it into Verilog. ! We are constraining you to a subset of the language for two reasons  Reduce complexity for the course  These are parts that people use to design real processors L02-2 Courtesy of Arvind Courtesy of Arvind http://csg.csail.mit.edu/6.375/L02-3 Courtesy of Arvind http://csg.csail.mit.edu/6.375/ Verilog Fundamentals ! History of hardware design languages ! Data types ! Structural Verilog ! Simple behaviors FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); endmoduleL02-4 Courtesy of Arvind http://csg.csail.mit.edu/6.375/ Bit-vector is the only data type in Verilog High impedance, floating Z Unknown logic value X Logic one 1 Logic zero 0 Meaning Value An X bit might be a 0, 1, Z, or in transition. We can set bits to be X in situations where we don’t care what the value is. This can help catch bugs and improve synthesis quality. A bit can take on one of four values • In the simulation waveform viewer, Unknown signals are RED. There should be no red after resetL02-5 Courtesy of Arvind http://csg.csail.mit.edu/6.375/ “wire” is used to denote a hardware net wire [15:0] instruction; wire [15:0] memory_req; wire [ 7:0] small_net; instruction memory_req instruction small_net ? Absolutely no type safety when connecting nets!L02-6 Courtesy of Arvind http://csg.csail.mit.edu/6.375/ Bit literals ! Binary literals  8’b0000_0000  8’b0xx0_1xx1 ! Hexadecimal literals  32’h0a34_def1  16’haxxx ! Decimal literals  32’d42 4’b10_11 Underscores are ignored Base format (d,b,o,h)󳆒 Decimal number representing size in bits We’ll learn how to actually assign literals to nets a little laterL02-7 Courtesy of Arvind http://csg.csail.mit.edu/6.375/ Verilog Fundamentals ! History of hardware design languages ! Data types ! Structural Verilog ! Simple behaviors FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); endmoduleOur Verilog Subset ! Verilog is a big language with many features not concerned with synthesizing hardware. ! The code you write for your processor should only contain the languages structures discussed in these slides. ! Anything else is not synthesizable, although it will simulate fine. ! You MUST follow the course coding standard L02-8 Courtesy of Arvind http://csg.csail.mit.edu/6.375/L02-9 Courtesy of Arvind http://csg.csail.mit.edu/6.375/ A Verilog module has a name and a port list adder A B sum cout module adder( input [3:0] A, input [3:0] B, output cout, output [3:0] sum ); // HDL modeling of // adder functionality endmodule Note the semicolon at the end of the port list! Ports must have a direction (or be bidirectional) and a bitwidth 4 4 4L02-10 Courtesy of Arvind http://csg.csail.mit.edu/6.375/ A module can instantiate other modules adder A B S cout FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( ... ); FA fa1( ... ); FA fa2( ... ); FA fa3( ... ); endmodule module FA( input a, b, cin output cout, sum ); // HDL modeling of 1 bit // full adder functionality endmodule FA b a c cin coutL02-11 Courtesy of Arvind http://csg.csail.mit.edu/6.375/ Connecting modules adder A B S cout FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); endmodule Carry ChainL02-12 Courtesy of Arvind http://csg.csail.mit.edu/6.375/ Alternative syntax Connecting ports by ordered list FA fa0( A[0], B[0], 1’b0, c0, S[0] ); Connecting ports by name (compact) FA fa0( .a(A[0]), .b(B[0]), .cin(1’b0), .cout(c0), .sum(S[0]) ); Argument order does not matter when ports are connected by name FA fa0 ( .a (A[0]), .cin (1’b0), .b (B[0]), .cout (c0), .sum (S[0]) ); Connecting ports by name yields clearer and less buggy code.L02-13 Courtesy of Arvind http://csg.csail.mit.edu/6.375/ Verilog Fundamentals ! History of hardware design languages ! Data types ! Structural Verilog ! Simple behaviors FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); endmoduleCourtesy of Arvind http://csg.csail.mit.edu/6.375/ L02-14 A module’s behavior can be described in many different ways but it should not matter from outside Example: mux4L02-15 Courtesy of Arvind http://csg.csail.mit.edu/6.375/ module mux4( input a, b, c, d input [1:0] sel, output out ); wire out, t0, t1; assign out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) ); assign t1 = ~( (sel[1] & d) | (~sel[1] & b) ); assign t0 = ~( (sel[1] & c) | (~sel[1] & a) ); endmodule mux4: Using continuous assignments The order of these continuous assignment statements does not matter. They essentially happen in parallel! Language defined operatorsL02-16 Courtesy of Arvind http://csg.csail.mit.edu/6.375/ mux4: Behavioral style // Four input multiplexer module mux4( input a, b,