Verilog 1 Fundamentals FA FA FA FA module adder input 3 0 A B output cout output 3 0 S wire c0 c1 c2 FA fa0 A 0 B 0 FA fa1 A 1 B 1 FA fa2 A 2 B 2 FA fa3 A 3 B 3 1 b0 c0 c1 c2 c0 c1 c2 cout S 0 S 1 S 2 S 3 endmodule 6 375 Complex Digital Systems Arvind Courtesy of Arvind http csg csail mit edu 6 375 L02 1 What is Verilog Verilog is a hardware description language There is more to it than that but this is what we will use it for In this class Verilog is an implementation language not a design language When you sit down to write verilog you should know exactly what you are implementing Draw your schematic and state machines and transcribe it into Verilog We are constraining you to a subset of the language for two reasons Reduce complexity for the course These are parts that people use to design real processors Courtesy of Arvind Courtesy of Arvind http csg csail mit edu 6 375 L02 2 Verilog Fundamentals History of hardware design languages Data types Structural Verilog Simple behaviors FA FA FA FA module adder input 3 0 A B output cout output 3 0 S wire c0 c1 c2 FA fa0 A 0 B 0 FA fa1 A 1 B 1 FA fa2 A 2 B 2 FA fa3 A 3 B 3 1 b0 c0 c1 c2 c0 c1 c2 cout S 0 S 1 S 2 S 3 endmodule Courtesy of Arvind http csg csail mit edu 6 375 L02 3 Bit vector is the only data type in Verilog A bit can take on one of four values Value Meaning 0 Logic zero 1 Logic one X Unknown logic value Z High impedance floating In the simulation waveform viewer Unknown signals are RED There should be no red after reset An X bit might be a 0 1 Z or in transition We can set bits to be X in situations where we don t care what the value is This can help catch bugs and improve synthesis quality Courtesy of Arvind http csg csail mit edu 6 375 L02 4 wire is used to denote a hardware net Courtesy of Arvind http csg csail mit edu 6 375 Absolutely no type safety when connecting nets small net instruction memory req instruction wire 15 0 instruction wire 15 0 memory req wire 7 0 small net L02 5 Bit literals 4 b10 11 Underscores are ignored Base format d b o h Decimal number representing size in bits Binary literals 8 b0000 0000 8 b0xx0 1xx1 Hexadecimal literals 32 h0a34 def1 16 haxxx Decimal literals 32 d42 We ll learn how to actually assign literals to nets a little later Courtesy of Arvind http csg csail mit edu 6 375 L02 6 Verilog Fundamentals History of hardware design languages Data types Structural Verilog Simple behaviors FA FA FA FA module adder input 3 0 A B output cout output 3 0 S wire c0 c1 c2 FA fa0 A 0 B 0 FA fa1 A 1 B 1 FA fa2 A 2 B 2 FA fa3 A 3 B 3 1 b0 c0 c1 c2 c0 c1 c2 cout S 0 S 1 S 2 S 3 endmodule Courtesy of Arvind http csg csail mit edu 6 375 L02 7 Our Verilog Subset Verilog is a big language with many features not concerned with synthesizing hardware The code you write for your processor should only contain the languages structures discussed in these slides Anything else is not synthesizable although it will simulate fine You MUST follow the course coding standard Courtesy of Arvind http csg csail mit edu 6 375 L02 8 A Verilog module has a name and a port list A B 4 4 adder 4 cout module adder input 3 0 A input 3 0 B output cout output 3 0 sum HDL modeling of adder functionality endmodule sum Ports must have a direction or be bidirectional and a bitwidth Courtesy of Arvind http csg csail mit edu 6 375 Note the semicolon at the end of the port list L02 9 A module can instantiate other modules A B adder cout FA FA FA S module adder input 3 0 A B output cout output 3 0 S wire c0 c1 c2 FA fa0 FA fa1 FA fa2 FA fa3 endmodule FA a cout FA b cin c module FA input a b cin output cout sum HDL modeling of 1 bit full adder functionality endmodule Courtesy of Arvind http csg csail mit edu 6 375 L02 10 Connecting modules A B adder cout FA FA FA FA S module adder input 3 0 A B output cout output 3 0 S wire c0 c1 c2 FA fa0 A 0 B 0 FA fa1 A 1 B 1 FA fa2 A 2 B 2 FA fa3 A 3 B 3 endmodule 1 b0 c0 c1 c2 Courtesy of Arvind http csg csail mit edu 6 375 c0 S 0 c1 S 1 c2 S 2 cout S 3 Carry Chain L02 11 Alternative syntax Connecting ports by ordered list FA fa0 A 0 B 0 1 b0 c0 S 0 Connecting ports by name compact FA fa0 a A 0 b B 0 cin 1 b0 cout c0 sum S 0 Argument order does not matter when ports are connected by name FA fa0 a cin b cout sum A 0 1 b0 B 0 c0 S 0 Connecting ports by name yields clearer and less buggy code Courtesy of Arvind http csg csail mit edu 6 375 L02 12 Verilog Fundamentals History of hardware design languages Data types Structural Verilog Simple behaviors FA FA FA FA module adder input 3 0 A B output cout output 3 0 S wire c0 c1 c2 FA fa0 A 0 B 0 FA fa1 A 1 B 1 FA fa2 A 2 B 2 FA fa3 A 3 B 3 1 b0 c0 c1 c2 c0 c1 c2 cout S 0 S 1 S 2 S 3 endmodule Courtesy of Arvind http csg csail mit edu 6 375 L02 13 A module s behavior can be described in many different ways but it should not matter from outside Example mux4 Courtesy of Arvind http csg csail mit edu 6 375 L02 14 mux4 Using continuous assignments module mux4 input a b c d input 1 0 sel output out Language defined operators wire out t0 t1 assign out t0 sel 0 t1 sel 0 assign t1 sel 1 d sel 1 b assign t0 sel 1 c sel 1 a endmodule The order of these continuous assignment statements does not matter They essentially happen in parallel Courtesy of Arvind http csg csail mit edu 6 375 L02 15 mux4 Behavioral style Four input multiplexer module mux4 input a b c d input 1 0 sel output out assign out endmodule sel sel sel sel 0 1 2 3 a b c d 1 bx If input is undefined we want …