1Week 4 UpdateCSE141LOctober 24, 2008Announcements• Most people haven’t e-mailed me theirpartner info :(• Lab 2, Part B due NEXT Friday (Noon)– Don’t wait until you are done with 141!• Schedule gets a lot tougher soon• Lab 3, Part A due in 2 weeks (Nov. 7)– We’ll talk about this some today2Tentative Schedule• Lab 2, Part B: Fetch Unit Control– Due Oct. 31• Lab 3, Part A: Exec datapath– Due Nov. 7• Lab 3, Part B: Exec control/test– Due Nov. 14(Prelim), 21 (Final)• Thanksgiving - Nov. 27• Lab 4: Benchmark/optimize Processor– Due Dec. 3• Demos will come shortly thereafterLab 2, Part B Questions?• I’ve been hearing crickets chirping onthe webboard3Lab 3, Part A• Design the datapath of the processor– Revisit the fetch unit– Design the datapath of the backend– Implement the datapath of the processorusing structural VerilogThe “Big Picture”• Decoupled Design– At least two stage pipeline• Backend– Single-, multi-, or pipelined?FrontendBackendFIFOFIFOFIFOFIFOFIFOFIFOFIFOFIFOFIFOFIFOFIFO……4Fetch Unit, Revisited• Fetch unit should require little change– Get creative, if you need• Major change: Instruction Memory– Increase size to 8K half-words• Previously only 1K half-words• Increases the address space (13 bits now)– Impacts?• Generate new module with C OREGen5Backend Components• Register File• Data Memory– Separate from instruction memory• Misc. logic components– ALU– Sign extender– MUX• Will be “leaf” modules to be instantiated in backendRegister File• Read : combinational logic• Write : sequential logic• Easily implemented by usingflip-flops• Sample interface:module regfile#(parameter SEL_WIDTH = 4, D_WIDTH = 34) { input clk, input we, input [SEL_WIDTH-1 : 0] read_sel, input [SEL_WIDTH-1 : 0] write_sel, input [D_WIDTH-1 : 0] din, output [D_WIDTH-1 : 0] dout } doutregfileread_seldinwewrite_sel6Data Memory• Use ‘CORE Generator’– Optimized implementation– Initialize with your ‘*.coe’ file– 8K addresses, 34-bit words– Tutorial is available on class website• Wrapper– Provides general interface– Read XOR Write– ‘refused’ signal?• Must try req againdmemGeneratedRam Modulewrite_enread_write_reqdindoutrefusedWrapperaddrThe Backend Datapathregfiledoutread_seldinwewrite_sel?dmemGeneratedRam Modulewrite_enread_write_reqdindoutrefusedWrapperaddr7I/O InterfaceBackendin_req, out_reqin_addr [3:0], out_addr [3:0]in_data [33:0]out_data [33:0]in_ack out_ackclock cycleout_req <= 1out_addr <= channeldout <= data…‘out’ completes…out_ack == 0 out_ack == 1in_req <= 1in_addr <= channel…reg[rt] <= din‘in’ completes…in_ack == 0in_ack == 1inoutPart A Deliverables• “Leaf” Modules– Reg File, Data Mem, etc.– Implemented with RTL Verilog• Execution Unit Datapath– Implemented with structural Verilog• Datapath Schematic– Do NOT use Xilinx schematic generator– Explain how instructions go through the
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