Week 4 Update CSE141L October 24 2008 Announcements Most people haven t e mailed me their partner info Lab 2 Part B due NEXT Friday Noon Don t wait until you are done with 141 Schedule gets a lot tougher soon Lab 3 Part A due in 2 weeks Nov 7 We ll talk about this some today 1 Tentative Schedule Lab 2 Part B Fetch Unit Control Due Oct 31 Lab 3 Part A Exec datapath Due Nov 7 Lab 3 Part B Exec control test Due Nov 14 Prelim 21 Final Thanksgiving Nov 27 Lab 4 Benchmark optimize Processor Due Dec 3 Demos will come shortly thereafter Lab 2 Part B Questions I ve been hearing crickets chirping on the webboard 2 Lab 3 Part A Design the datapath of the processor Revisit the fetch unit Design the datapath of the backend Implement the datapath of the processor using structural Verilog The Big Picture Decoupled Design At least two stage pipeline Backend Single multi or pipelined Frontend FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO Backend 3 Fetch Unit Revisited Fetch unit should require little change Get creative if you need Major change Instruction Memory Increase size to 8K half words Previously only 1K half words Increases the address space 13 bits now Impacts Generate new module with COREGen 4 Backend Components Register File Data Memory Separate from instruction memory Misc logic components ALU Sign extender MUX Will be leaf modules to be instantiated in backend Register File Read combinational logic we Write sequential logic write sel Easily implemented by using din flip flops read sel Sample interface regfile dout module regfile parameter SEL WIDTH 4 D WIDTH 34 input clk input we input SEL WIDTH 1 0 read sel input SEL WIDTH 1 0 write sel input D WIDTH 1 0 din output D WIDTH 1 0 dout 5 Data Memory Use CORE Generator Optimized implementation Initialize with your coe file 8K addresses 34 bit words Tutorial is available on class website read write req Wrapper write en Provides general interface Read XOR Write refused signal addr dout Generated Ram Module dmem din refused Must try req again Wrapper The Backend Datapath we write sel din regfile dout read sel read write req write en addr din Generated Ram Module dout dmem refused Wrapper 6 I O Interface in req out req in addr 3 0 out addr 3 0 in data 33 0 out data 33 0 in ack out ack Backend clock cycle in ack 0 in in req 1 in addr channel out out req 1 out addr channel dout data out ack 0 in ack 1 reg rt din in completes out ack 1 out completes Part A Deliverables Leaf Modules Reg File Data Mem etc Implemented with RTL Verilog Execution Unit Datapath Implemented with structural Verilog Datapath Schematic Do NOT use Xilinx schematic generator Explain how instructions go through the datapath 7 Questions 8
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