Application Note Test Benches R Writing Efficient Testbenches Author Mujtaba Hamid XAPP199 v1 0 June 11 2001 Summary This application note is written for logic designers who are new to HDL verification flows and who do not have extensive testbench writing experience Testbenches are the primary means of verifying HDL designs This application note provides guidelines for laying out and constructing efficient testbenches It also provides an algorithm to develop a self checking testbench for any design All design files for this application note are available on the FTP site at PC ftp ftp xilinx com pub applications xapp xapp199 zip UNIX ftp ftp xilinx com pub applications xapp xapp199 tar gz Introduction Due to increases in design size and complexity digital design verification has become an increasingly difficult and laborious task To meet this challenge verification engineers rely on several verification tools and methods For large multi million gate designs engineers typically use a suite of formal verification tools However for smaller designs design engineers usually find that HDL simulators with testbenches work best Testbenches have become the standard method to verify HLL High Level Language designs Typically testbenches perform the following tasks Instantiate the design under test DUT Stimulate the DUT by applying test vectors to the model Output results to a terminal or waveform window for visual inspection Optionally compare actual results to expected results Typically testbenches are written in the industry standard VHDL or Verilog hardware description languages Testbenches invoke the functional design then stimulate it Complex testbenches perform additional functions for example they contain logic to determine the proper design stimulus for the design or to compare actual to expected results The remaining sections of this note describe the structure of a well composed testbench and provide an example of a self checking testbench one that automates the comparison of actual to expected testbench results Figure 1 shows a standard HDL verification flow which follows the steps outlined above Since testbenches are written in VHDL or Verilog testbench verification flows can be ported across platforms and vendor tools Also since VHDL and Verilog are standard non proprietary 2000 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm All other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice XAPP199 v1 0 June 11 2001 www xilinx com 1 800 255 7778 1 R Writing Efficient Testbenches languages verification suites written in VHDL or Verilog can be reused in future designs without difficulty Testbench Verification Flow Testbench Displays Values on Terminal Testbench Instantiates Design and Provides Stimulus Verify Result on Waveform Design Under Test DUT Testbench Checks for Correctness XAPP199 01 042001 Figure 1 HDL Verification Flow Using Testbenches Constructing Testbenches Testbenches can be written in VHDL or Verilog Since testbenches are used for simulation only they are not limited by semantic constraints that apply to RTL language subsets used in synthesis Instead all behavioral constructs can be used Thus testbenches can be written more generically making them easier to maintain All testbenches contain the basic sections shown in Table 1 As mentioned above testbenches typically contain additional functionality as well such as the visual display of results on a terminal and built in error detection Table 1 Sections Common to Testbenches VHDL Verilog Entity and Architecture Declaration Module Declaration Signal Declaration Signal Declaration Instantiation of Top level Design Instantiation of Top level Design Provide Stimulus Provide Stimulus The following examples show some constructs used frequently in testbenches Generating Clock Signals Designs that use system clocks to sequence logic must generate a clock Iterative clocks can easily be implemented in both VHDL and Verilog source code The following are VHDL and Verilog examples of clock generation VHDL Declare a clock period constant Constant ClockPeriod TIME 10 ns Clock Generation method 1 Clock not Clock after ClockPeriod 2 Clock Generation method 2 GENERATE CLOCK process begin 2 www xilinx com 1 800 255 7778 XAPP199 v1 0 June 11 2001 R Writing Efficient Testbenches wait for ClockPeriod 2 Clock 1 wait for ClockPeriod 2 Clock 0 end process Verilog Declare a clock period constant Parameter ClockPeriod 10 Clock Generation method 1 initial begin forever Clock ClockPeriod 2 Clock end Clock Generation method 2 initial begin always ClockPeriod 2 Clock Clock end Providing Stimulus To obtain testbench verification results stimulus must be provided to the DUT Concurrent stimulus blocks are used in testbenches to provide the necessary stimuli Two methods are employed absolute time stimulus and relative time stimulus In the first method simulation values are specified relative to simulation time zero By comparison relative time stimulus supplies initial values then waits for an event before retriggering the stimulus Both methods can be combined in a testbench according to the designer s needs Table 2 and Table 3 provide examples of absolute time and relative time stimuli respectively in VHDL and Verilog source code Table 2 Absolute Time Stimulus Example VHDL ABSOLUTE TIME MainStimulus process begin Reset 1 Load 0 Count UpDn 0 wait for 100 ns Reset 0 wait for 20 ns Load 1 wait for 20 ns Count UpDn 1 end process XAPP199 v1 0 June 11 2001 www xilinx com 1 800 255 7778 Verilog ABSOLUTE TIME initial begin Reset 1 Load 0 Count UpDn 0 100 Reset 0 20 Load 1 20 Count UpDn 1 end 3 R Writing Efficient Testbenches Table 3 Relative Time Stimulus Example VHDL RELATIVE TIME Process Clock Begin If rising edge Clock then TB Count TB Count 1 end if end process SecondStimulus process begin if TB Count 5 then Reset 1 Load 0 Count UpDn 0 Else Reset 0 Load 1 Count UpDn 1 end process FinalStimulus process begin if Count 1100 then Count UpDn 0 report Terminal Count Reached now counting down end if end process Verilog RELATIVE TIME always posedge clock TB Count TB Count 1 initial begin if TB Count 5 begin Reset 1 Load 0 Count UpDn 0 end else begin Reset 0 Load 1 Count UpDn 1 end end initial begin if Count 1100 begin Count UpDn 0 display Terminal Count Reached now counting down end