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UCSD CSE 141L - Writing Efficient Testbenches

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SummaryIntroductionConstructing TestbenchesGenerating Clock SignalsVHDL:Verilog:Providing StimulusDisplaying ResultsSimple TestbenchesVerilog Example:VHDL Example:Automatic VerificationSelf-Checking TestbenchesVerilog ExampleVHDL ExampleGuidelines for Writing TestbenchesXilinx Simulation Flow TipsConfiguration Statement (VHDL)Initializing Block RAMs for SimulationAdvanced Testbench TechniquesBreaking Up Stimulus Blocks with Tasks and ProceduresVerilog Example:VHDL Example:Controlling Bidirectional Signals in SimulationVHDL Example:Verilog Example:Initializing Memory for SimulationUseful Language ConstructsVerilogforce/releaseassign/deassigntimescalesReading Memory Initialization FilesVHDLmeminitfileCoding Style GuidelinesIndentationFile NamingSignal NamingCommentingDesign StructureConclusionRevision HistoryXAPP199 (v1.0) June 11, 2001 www.xilinx.com 11-800-255-7778© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.Summary This application note is written for logic designers who are new to HDL verification flows, and who do not have extensive testbench-writing experience.Testbenches are the primary means of verifying HDL designs. This application note provides guidelines for laying out and constructing efficient testbenches. It also provides an algorithm to develop a self-checking testbench for any design. All design files for this application note are available on the FTP site at:PC: ftp://ftp.xilinx.com/pub/applications/xapp/xapp199.zipUNIX: ftp://ftp.xilinx.com/pub/applications/xapp/xapp199.tar.gzIntroduction Due to increases in design size and complexity, digital design verification has become an increasingly difficult and laborious task. To meet this challenge, verification engineers rely on several verification tools and methods. For large, multi-million gate designs, engineers typically use a suite of formal verification tools. However, for smaller designs, design engineers usually find that HDL simulators with testbenches work best.Testbenches have become the standard method to verify HLL (High-Level Language) designs. Typically, testbenches perform the following tasks:• Instantiate the design under test (DUT)• Stimulate the DUT by applying test vectors to the model• Output results to a terminal or waveform window for visual inspection• Optionally compare actual results to expected resultsTypically, testbenches are written in the industry-standard VHDL or Verilog hardware description languages. Testbenches invoke the functional design, then stimulate it. Complex testbenches perform additional functions—for example, they contain logic to determine the proper design stimulus for the design or to compare actual to expected results.The remaining sections of this note describe the structure of a well-composed testbench, and provide an example of a self-checking testbench—one that automates the comparison of actual to expected testbench results.Figure 1 shows a standard HDL verification flow which follows the steps outlined above.Since testbenches are written in VHDL or Verilog, testbench verification flows can be ported across platforms and vendor tools. Also, since VHDL and Verilog are standard non-proprietary Application Note: Test BenchesXAPP199 (v1.0) June 11, 2001Writing Efficient TestbenchesAuthor: Mujtaba HamidR2 www.xilinx.com XAPP199 (v1.0) June 11, 20011-800-255-7778Writing Efficient TestbenchesRlanguages, verification suites written in VHDL or Verilog can be reused in future designs without difficulty.Constructing TestbenchesTestbenches can be written in VHDL or Verilog. Since testbenches are used for simulation only, they are not limited by semantic constraints that apply to RTL language subsets used in synthesis. Instead, all behavioral constructs can be used. Thus, testbenches can be written more generically, making them easier to maintain.All testbenches contain the basic sections shown in Table 1. As mentioned, above, testbenches typically contain additional functionality as well, such as the visual display of results on a terminal and built-in error detection. The following examples show some constructs used frequently in testbenches.:Generating Clock SignalsDesigns that use system clocks to sequence logic must generate a clock. Iterative clocks can easily be implemented in both VHDL and Verilog source code. The following are VHDL and Verilog examples of clock generation:VHDL:-- Declare a clock period constant.Constant ClockPeriod : TIME := 10 ns;-- Clock Generation method 1:Clock <= not Clock after ClockPeriod / 2;-- Clock Generation method 2:GENERATE CLOCK: processbeginFigure 1: HDL Verification Flow Using TestbenchesTestbench Verification FlowTestbench Instantiates Designand Provides StimulusDesign Under Test(DUT)TestbenchDisplays Valueson TerminalVerify Resulton WaveformTestbenchChecks forCorrectnessXAPP199_01_042001Table 1: Sections Common to TestbenchesVHDL VerilogEntity and Architecture Declaration Module DeclarationSignal Declaration Signal DeclarationInstantiation of Top-level Design Instantiation of Top-level DesignProvide Stimulus Provide StimulusWriting Efficient TestbenchesXAPP199 (v1.0) June 11, 2001 www.xilinx.com 31-800-255-7778Rwait for (ClockPeriod / 2)Clock <= ’1’;wait for (ClockPeriod / 2)Clock <= ’0’;end process;Verilog:// Declare a clock period constant.Parameter ClockPeriod = 10;// Clock Generation method 1:initial beginforever Clock = #(ClockPeriod / 2) ~ Clock;end// Clock Generation method 2:initial beginalways #(ClockPeriod / 2) Clock = ~Clock;endProviding StimulusTo obtain testbench verification results, stimulus must be provided to the DUT. Concurrent stimulus blocks are used in testbenches to provide the necessary stimuli. Two methods are employed: absolute-time stimulus and relative-time stimulus. In the first method, simulation values are specified relative to simulation time zero. By comparison, relative-time stimulus supplies initial values, then waits for an event before retriggering the stimulus. Both methods can be combined in a testbench, according to the designer’s needs.Table 2 and Table 3 provide examples of absolute-time and relative-time stimuli, respectively, in VHDL and Verilog source code.Table 2: Absolute Time Stimulus


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