Verilog 2 Design Examples 6 375 Complex Digital Systems Arvind February 9 2009 February 9 2009 Courtesy of Arvind http csg csail mit edu 6 375 L03 1 Verilog Design Examples Greatest Common Divisor February 9 2009 Courtesy of Arvind http csg csail mit edu 6 375 L03 2 What does the RTL implementation need GCD in C int GCD int inA int inB inputs int done 0 int A inA State int B inB while done iteration if A B Less Than Comparator swap A A B Swap B swap else if B 0 Equal Comparator A A B else Subtractor done 1 Termination control return A output February 9 2009 Courtesy of Arvind http csg csail mit edu 6 375 L03 3 Step 1 Design an appropriate port interface input available result rdy idle result taken operand A result data operand B clk February 9 2009 reset Courtesy of Arvind http csg csail mit edu 6 375 L03 4 Step 2 Design a datapath which has the functional units zero lt A inA B inB A sub B February 9 2009 Courtesy of Arvind http csg csail mit edu 6 375 while done begin if A B swap A A B B swap else if B 0 A A B else done 1 End Y A L03 5 Step 3 Add the control unit Control unit to sequence the datapath should be A A sel en B B sel en B 0 A B zero lt designed to be either busy or waiting for input or waiting for output to be picked up A inA B inB A sub B February 9 2009 Courtesy of Arvind http csg csail mit edu 6 375 while done begin if A B swap A A B B swap else if B 0 A A B else done 1 End Y A L03 6 Datapath module interface module GCDdatapath parameter W 16 input clk Data signals input W 1 0 operand A input W 1 0 operand B output W 1 0 result data Control signals ctrl dpath input A en input B en input 1 0 A sel input B sel A A sel en B B sel en A B 0 A B zero lt sub B Control signals dpath ctrl output B zero output A lt B February 9 2009 Courtesy of Arvind http csg csail mit edu 6 375 L03 7 Connect the modules wire W 1 0 B wire W 1 0 sub out wire W 1 0 A out vcMux3 W A mux in0 operand A in1 B in2 sub out sel A sel out A out A A sel en B B sel en A B 0 A B zero lt sub B wire W 1 0 A vcEDFF pf W A pf clk clk en p A en d p A out q np A February 9 2009 Courtesy of Arvind http csg csail mit edu 6 375 L03 8 Connect the modules wire W 1 0 B wire W 1 0 sub out wire W 1 0 A out vcMux3 W A mux in0 operand A in1 B in2 sub out sel A sel out A out wire W 1 0 A vcEDFF pf W A pf clk clk en p A en d p A out q np A February 9 2009 Using explicit state helps vcMux2 W B mux eliminate issues in0 operand B with non blocking in1 A assignments wire W 1 0 B out sel B sel out B out vcEDFF pf W B pf Continuous clk clk assignment en p B en combinational d p B out logic is fine q np B assign B zero B 0 assign A lt B A B assign sub out A B assign result data A Courtesy of Arvind http csg csail mit edu 6 375 L03 9 Control unit requires a state machine for valid ready signals reset WAIT Waiting for new input operands input availble CALC Swapping and subtracting B 0 result taken DONE February 9 2009 Waiting for consumer to take the result Courtesy of Arvind http csg csail mit edu 6 375 L03 10 Implementing the control logic FSM in Verilog localparam WAIT 2 d0 localparam CALC 2 d1 localparam DONE 2 d2 reg 1 0 state next wire 1 0 state Localparams are not really parameters at all They are scoped constants always posedge clk begin state state next end February 9 2009 Courtesy of Arvind http csg csail mit edu 6 375 L03 11 Control signals for the FSM reg 6 0 cs WAIT begin always A sel A SEL IN begin A en 1 b1 Default control signals B sel B SEL IN A sel A SEL X B en 1 b1 A en 1 b0 input available 1 b1 B sel B SEL X end B en 1 b0 CALC if A lt B input available 1 b0 A sel A SEL B result rdy 1 b0 A en 1 b1 case state B sel B SEL A WAIT B en 1 b1 else if B zero CALC A sel A SEL SUB A en 1 b1 DONE end DONE result rdy 1 b1 endcase Courtesy of Arvind http end February 9 2009 csg csail mit edu 6 375 L03 12 FSM state transitions always begin reset Default is to stay in the same state state next state case state WAIT if input available state next CALC CALC if B zero state next DONE DONE if result taken state next WAIT endcase end February 9 2009 WAIT input availble CALC B 0 result taken Courtesy of Arvind http csg csail mit edu 6 375 DONE L03 13 RTL test harness requires proper handling of the ready valid signals A A sel en Generic Test Source B B sel en B 0 A B zero lt A sub B February 9 2009 Courtesy of Arvind http csg csail mit edu 6 375 Generic Test Sink L03 14