ISE In-Depth TutorialAbout This TutorialAbout the In-Depth TutorialTutorial ContentsTutorial FlowsHDL Design FlowSchematic Design FlowImplementation-only FlowAdditional ResourcesTable of ContentsOverview of ISEOverview of ISEProject Navigator InterfaceDesign PanelFiles PanelLibraries PanelConsole PanelErrors PanelWarnings PanelWorkspaceDesign Summary & Report ViewerUsing Project Revision Management FeaturesISE Project FileMaking a Copy of a ProjectUsing the Project BrowserUsing Project ArchivesHDL-Based DesignOverview of HDL-Based DesignGetting StartedRequired SoftwareOptional Software RequirementsVHDL or Verilog?Installing the Tutorial Project FilesStarting the ISE SoftwareCreating a New ProjectStopping the TutorialDesign DescriptionInputsOutputsFunctional BlocksDesign EntryAdding Source FilesChecking the SyntaxCorrecting HDL ErrorsCreating an HDL-Based ModuleCreating a CORE Generator ModuleCreating a DCM ModuleSynthesizing the DesignSynthesizing the Design using XSTSynthesizing the Design using Synplify/Synplify ProSynthesizing the Design Using Precision SynthesisSchematic-Based DesignOverview of Schematic-Based DesignGetting StartedRequired SoftwareInstalling the Tutorial Project FilesStarting the ISE SoftwareCreating a New ProjectStopping the TutorialDesign DescriptionInputsOutputsFunctional BlocksDesign EntryOpening the Schematic File in the Xilinx Schematic EditorManipulating the Window ViewCreating a Schematic-Based MacroDefining the time_cnt SchematicCreating and Placing the time_cnt SymbolCreating a CORE Generator ModuleCreating a DCM ModuleCreating the dcm1 SymbolCreating an HDL-Based ModuleCreating Schematic Symbols for HDL modulesPlacing the statmach, timer_preset, dcm1 and debounce SymbolsChanging Instance NamesHierarchy Push/PopSpecifying Device Inputs/OutputsAssigning Pin LocationsCompleting the SchematicBehavioral SimulationOverview of Behavioral Simulation FlowModelSim SetupModelSim PE and SEModelSim Xilinx EditionISim SetupGetting StartedRequired FilesXilinx Simulation LibrariesAdding an HDL Test BenchAdding Tutorial Test Bench FileBehavioral Simulation Using ModelSimLocating the Simulation ProcessesSpecifying Simulation PropertiesPerforming SimulationAdding SignalsSaving the SimulationBehavioral Simulation Using ISimLocating the Simulation ProcessesSpecifying Simulation PropertiesPerforming SimulationAdding SignalsRerunning SimulationDesign ImplementationOverview of Design ImplementationGetting StartedContinuing from Design EntryStarting from Design ImplementationSpecifying OptionsCreating Timing ConstraintsTranslating the DesignUsing the Constraints EditorAssigning I/O Locations Using PlanAheadMapping the DesignUsing Timing Analysis to Evaluate Block Delays After MappingEstimating Timing Goals with the 50/50 RuleReport Paths in Timing Constraints OptionPlacing and Routing the DesignUsing FPGA Editor to Verify the Place and RouteEvaluating Post-Layout TimingViewing the Post-Place & Route Static Timing ReportAnalyzing the Design using PlanAheadCreating Configuration DataCreating a PROM File with iMPACTCommand Line ImplementationTiming SimulationOverview of Timing Simulation FlowGetting StartedRequired SoftwareRequired FilesSpecifying a SimulatorTiming Simulation Using ModelSimSpecifying Simulation Process PropertiesPerforming SimulationTiming Simulation Using Xilinx ISimSpecifying Simulation Process PropertiesPerforming SimulationiMPACT TutorialDevice SupportDownload Cable SupportParallel Cable IVPlatform Cable USBMultiPRO CableConfiguration Mode SupportGetting StartedGenerating the Configuration FilesConnecting the CableStarting the SoftwareCreating a iMPACT New Project FileUsing Boundary Scan Configuration ModeSpecifying Boundary Scan Configuration ModeAssigning Configuration FilesSaving the Project FileEditing PreferencesPerforming Boundary Scan OperationsTroubleshooting Boundary Scan ConfigurationVerifying Cable ConnectionVerifying Chain SetupCreating an SVF FileSetting up Boundary Scan ChainWriting to the SVF FileStop Writing to the SVFPlaying back the SVF or XSVF fileOther Configuration ModesSlave Serial Configuration ModeSelectMAP Configuration ModeRISE In-Depth TutorialUG695 (v 11.2) June 24, 2009ISE 11 In-Depth Tutorial www.xilinx.comXilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.© 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.RISE 11 In-Depth Tutorial www.xilinx.com 3UG695 (v 11.2)RPrefaceAbout This TutorialAbout the In-Depth TutorialThis tutorial gives a description of the features and additions to Xilinx® ISE™ 11. The primary focus of this tutorial is to show the relationship among the design entry tools, Xilinx and third-party tools, and the design implementation tools.This guide is a learning tool for designers who are unfamiliar with the features of the ISE software or those wanting to refresh their skills and knowledge. You may choose to follow one of the three tutorial flows