ISE In Depth Tutorial UG695 v 11 2 June 24 2009 R R Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED 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implementation tools This guide is a learning tool for designers who are unfamiliar with the features of the ISE software or those wanting to refresh their skills and knowledge You may choose to follow one of the three tutorial flows available in this document For information about the tutorial flows see Tutorial Flows Tutorial Contents This guide covers the following topics ISE 11 In Depth Tutorial UG695 v 11 2 Chapter 1 Overview of ISE introduces you to the ISE primary user interface Project Navigator and the synthesis tools available for your design Chapter 2 HDL Based Design guides you through a typical HDL based design procedure using a design of a runner s stopwatch This chapter also shows how to use ISE accessories such as CORE Generator and ISE Text Editor Chapter 3 Schematic Based Design explains many different facets of a schematicbased ISE design flow using a design of a runner s stopwatch This chapter also shows how to use ISE accessories such as CORE Generator and ISE Text Editor Chapter 4 Behavioral Simulation explains how to simulate a design before design implementation to verify that the logic that you have created is correct Chapter 5 Design Implementation describes how to Translate Map Place Route and generate a Bit file for designs Chapter 6 Timing Simulation explains how to perform a timing simulation using the block and routing delay information from the routed design to give an accurate assessment of the behavior of the circuit under worst case conditions Chapter 7 iMPACT Tutorial explains how to program a device with a newly created design using the IMPACT configuration tool www xilinx com 3 R Preface About This Tutorial Tutorial Flows This document contains three tutorial flows In this section the three tutorial flows are outlined and briefly described in order to help you determine which sequence of chapters applies to your needs The tutorial flows include HDL Design Flow Schematic Design Flow Implementation only Flow HDL Design Flow The HDL Design flow is as follows Chapter 2 HDL Based Design Chapter 4 Behavioral Simulation Note that although behavioral simulation is optional it is strongly recommended in this tutorial flow Chapter 5 Design Implementation Chapter 6 Timing Simulation Note that although timing simulation is optional it is strongly recommended in this tutorial flow Chapter 7 iMPACT Tutorial Schematic Design Flow The Schematic Design flow is as follows Chapter 3 Schematic Based Design Chapter 4 Behavioral Simulation Note that although behavioral simulation is optional it is strongly recommended in this tutorial flow Chapter 5 Design Implementation Chapter 6 Timing Simulation Note that although timing simulation is optional it is strongly recommended Chapter 7 iMPACT Tutorial Implementation only Flow The Implementation only flow is as follows 4 Chapter 5 Design Implementation Chapter 6 Timing Simulation Note that although timing simulation is optional it is strongly recommended in this tutorial flow Chapter 7 iMPACT Tutorial www xilinx com ISE 11 In Depth Tutorial UG695 v 11 2 R Additional Resources Additional Resources To find additional documentation see the Xilinx website at http www xilinx com literature To search the Answer Database of silicon software and IP questions and answers or to create a technical support WebCase see the Xilinx website at http www xilinx com support ISE 11 In Depth Tutorial UG695 v 11 2 www xilinx com 5 R 6 Preface About This Tutorial www xilinx com ISE 11 In Depth Tutorial UG695 v 11 2 Table of Contents Preface About This Tutorial About the In Depth Tutorial 3 Tutorial Contents 3 Tutorial Flows 4 HDL Design Flow 4 Schematic Design Flow 4 Implementation only Flow 4 Additional Resources 5 Chapter 1 Overview of ISE Overview of ISE 13 Project Navigator Interface Design Panel Sources View Processes View Files Panel Libraries Panel Console Panel Errors Panel Warnings Panel Error Navigation to Source Error Navigation to Answer Record Workspace Design Summary Report Viewer 13 14 14 15 15 16 16 16 16 16 16 16 16 Using Project Revision Management Features 17 ISE Project File Making a Copy of a Project Using the Project Browser Using Project Archives Creating an Archive Restoring an Archive 17 17 18 18 18 18 Chapter 2 HDL Based Design Overview of HDL Based Design 19 Getting Started 19 Required Software Optional Software Requirements VHDL or Verilog Installing the Tutorial Project Files Starting the ISE Software Creating a New Project Creating a New Project Using