CSE 141L Computer Architecture Lab Fall 2005 Lecture 4 Pramod V Argade November15th 2005 Fall 2005 CSE 141L Course Schedule Lecture 1 2 3 4 5 6 7 8 9 CSE141 L 2 Date 9 27 10 4 10 11 10 18 10 25 11 1 11 8 11 15 11 22 11 29 12 2 Day Tuesday Tuesday Tuesday Tuesday Tuesday Tuesday Tuesday Tuesday Tuesday Lecture Topic No Class Lab1 8 bit Processo ISA Lab1 Discussion Lab2 Assembler ISS LogicWorks 5 Review Lab 3 Data Path Lab 3 Discussion Lab 4 Full CPU Lab4 Discussion Lab 4 Demo by Students Lab Due Lab1 Lab2 Lab3 Lab4 Pramod Argade Fall 05 1 Lab Due Dates Lab 4 Due Before 6 00 PM Tuesday November 29th You must make an appointment to demonstrate your between CPU November 29th through December 2nd You cannot make any changes to the design between the time you submit to your demo to TA No late submissions CSE141 L 3 Pramod Argade Fall 05 Microprocessor Design Steps 9Design Instruction Set Architecture ISA 9Develop software generation tools 9Code applications 9Develop instruction set simulator ISS 9Design datapath verify it Design the Processor simulate logic Verify the processor Fabricate the chip not in this class CSE141 L 4 Pramod Argade Fall 05 2 Lab 4 Assignment Design logic for complete 8 bit processor architecture Use LogicWorks 5 to design logic Simulate the operation executing 3 programs from Lab 1 CSE141 L 5 Pramod Argade Fall 05 Processor Organization CLK PC Note Blocks in your architecture equivalent to those in blue are to be implemented in Lab4 I Mem OPC DST SRC Instruction OPCODE CPU Control CLK Logic Control ALU OP Signals ALU Control Logic Register File D Mem 2 1 Multiplexor ALU 2 1 Multiplexor CSE141 L 6 Pramod Argade Fall 05 3 What you must include Reset logic Program Counter Logic Non control transfer instructions Control transfer instructions Halt instruction Data path modified for Load Store instructions Control logic Instruction counter Initialize on reset Freeze on HALT instruction CSE141 L 7 Pramod Argade Fall 05 What you will turn in for this Lab Summary of your ISA from Lab 1 and assembly code with machine code for 3 programs Printed schematics for the top level CPU in LogicWorks 5 All the LogicWorks 5 files you created to be submitted via electronic submission Answers to following questions CSE141 L 8 Pramod Argade Fall 05 4 Questions What changes did you make in your original ISA and why What is instruction count for each one of the three programs How do the numbers compare with those for the ISS If the numbers are different why What are the strengths of your design What are the deficiencies of your design Which instruction will determine the clock frequency of your processor i e is responsible for the critical path Which instruction is most expensive in terms of the number of gates required CSE141 L 9 Pramod Argade Fall 05 Question Continued Having gone through a complete CPU design experience what would you do differently in your ISA to Decrease static and dynamic instruction count Simplify data path design Simplify CPU design If you were to pipeline the execution what would the pipeline stages be Give at least three issues that will complicate the design of your processor CSE141 L 10 Pramod Argade Fall 05 5 Lab 4 Grading It is your responsibility to make an appointment with one of the TAs before 11 29 05 Show TA that your CPU design works before end of Friday December 2nd You should test the programs using the data patterns given in Lab1 The TAs may test your design for correct functionality using their own data files that satisfy the constraints outlined in Lab 1 CSE141 L 11 Pramod Argade Fall 05 Useful Hints Build hierarchical design Test thoroughly at every level of hierarchy Connect binary switches and hex keypads to provide inputs Connect binary and hex displays to observe behavior Write an assembly program to test individual instructions in your CPU Self checking programs are ideal CSE141 L 12 Pramod Argade Fall 05 6 What is Functional Verification Making sure that your design is functionally correct Reset behavior Instructions Addressing modes Algorithms in hardware e g setting carry Corner cases Control transfer branch jump Memory access Special features e g HALT in our case CSE141 L 13 Pramod Argade Fall 05 Importance of Verification General purpose processor must run without a flaw any application running on it Programmers will use the CPU in ways you never imagined Processor may be used in mission critical applications It is costly to fix bugs in processors Chip mask and fabrication costs System HW and SW redesign Lost market opportunity CSE141 L 14 Pramod Argade Fall 05 7 A Program to Test 8 bit CPU 0x3f 0000 start 0xb7 0001 0x5f 0002 0x8b 0003 0xae 0004 0xfb 0005 0x97 0006 0x08 0007 0x69 0008 0xd9 0009 0xe7 0010 0xa9 0011 0x7a 0012 0x33 0013 0x52 0014 0x40 0015 0x59 0016 0x79 0017 cont1 0x53 0018 0x52 0019 0x41 0020 0x43 0021 0xc9 0022 cont2 0x53 0023 0x52 0024 0x40 0025 0x43 0026 0xc6 0027 cont3 0x53 0028 0x53 0029 0x40 0030 0x51 0031 0x42 0032 0x43 0033 cont4 0x69 0034 cont5 0x6d 0035 0xfb 0035 CSE141 L 15 0x43 0036 CSE141 L 16 mov shl4 add mov ushr4 st add mov sub xor ld ushr4 cmpeq mov add jmpf add cmpeq add add jmpt halt cmphi add add jmpf halt cmphi add add jmpf add jmp halt sub sub st halt r3 r1 r3 r2 r3 r2 r1 r2 r2 r2 r1 r2 r2 r0 r0 r0 r2 r2 r0 r0 r0 0xf r3 3 r3 r2 r3 r3 0 1 r1 r3 r1 2 0xf 2 1 1 3 2 r2 r1 r0 3 r0 2 r0 r1 r2 r0 3 r0 3 cont4 r0 1 r0 r2 1 r3 1 r2 r3 r3 0xf r1 0xf0 r3 0x12 r2 0x12 r3 1 M 1 0x12 r1 0xf1 test curruption of RAM r2 0 r2 0xff r2 0xe r1 0x12 r2 1 flag 0 r0 0xf r0 0x11 addr of cont1 should jump should not exec r2 1 flag 1 r0 0x14 r0 0x16 address of cont2 jmp cont2 should not halt flag 0 r0 0x19 r0 0x1b should jump to cont3 should not halt flag 1 r0 0x1e r0 0x21 should not jump to cont4 r0 0x22 address of cont5 jump to cont5 should not halt r2 0 r3 0 M 0 0 Pramod Argade Fall 05 Pramod Argade Fall 05 8 Before you leave Remember to make appointment with the TAs to show your operational design CSE141 L 17 Pramod Argade Fall 05 9