1Week 7 UpdateCSE141LNov. 14, 2008Announcements• Upcoming schedule:– Lab 3A due today– Lab 3B Steps 1-3 due next Fri (Nov. 21)– Lab 3B Steps 4-7 due Mon, Dec. 1– Final Writeup due Wed, Dec. 3• Quick Poll– Who was able to simulate data mem?2Execution Unit Control and Test• Step 1: Implement control for executionunit• Step 2: Finalize fetch unit– Generate instruction mem (8K) and FIFO• Step 3: Test all instructions– Test program that uses all instructions inyour ISAStep 4: IO Test• VirtualMachine needs to load programsfrom external device– Use in and out instructions for this– We provide device (io_devices.v)• VirtualMachine emulates programswritten in “SuperGarbage” ISA3Communicate with Ext. Device• 3 input channels– #1 - Request next word in binary file– #2 - Request current clock count– #3 - Request input data from “input.txt”• 3 output channels– #1 - Select SuperGarbage binary file– #2 - Set clock count– #3 - Debug outputStep 5: SuperGarbage LoaderAddr 3Data 0Addr 0Data 1Addr 2Data n-13LoaderData 1Data Data nData 0Data Data Data Data VirtualMachine(startPC, mem);mem[]startPC0123sample.bin4Step 6: VirtualMachine Test• Test perf on sample SuperGarbage apps– Compare fibonacci– Counter in IO device allows us to benchmarkperformance• SuperGarbageSim simulates apps– go: execute instructions– disassembly: show disassembled instructions– getmem: print memory contents– setmem: set memory data– setPC– getPCSimulation Setup5Behavioral SimulationCorrectly work at any cycle time constraint*.mif file?Post-route SimulationSetting a proper cycle time is importantModification of RAM contents needs a re-creation of the
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