Week 7 Update CSE141L Nov 14 2008 Announcements Upcoming schedule Lab 3A due today Lab 3B Steps 1 3 due next Fri Nov 21 Lab 3B Steps 4 7 due Mon Dec 1 Final Writeup due Wed Dec 3 Quick Poll Who was able to simulate data mem 1 Execution Unit Control and Test Step 1 Implement control for execution unit Step 2 Finalize fetch unit Generate instruction mem 8K and FIFO Step 3 Test all instructions Test program that uses all instructions in your ISA Step 4 IO Test VirtualMachine needs to load programs from external device Use in and out instructions for this We provide device io devices v VirtualMachine emulates programs written in SuperGarbage ISA 2 Communicate with Ext Device 3 input channels 1 Request next word in binary file 2 Request current clock count 3 Request input data from input txt 3 output channels 1 Select SuperGarbage binary file 2 Set clock count 3 Debug output Step 5 SuperGarbage Loader sample bin mem Addr 3 Data 0 Addr 0 Data 1 Loader 0 Data 1 1 Data 2 Data n 3 Data 0 startPC Data Data Addr 2 Data n Data VirtualMachine startPC mem Data 1 3 3 Step 6 VirtualMachine Test Test perf on sample SuperGarbage apps Compare fibonacci Counter in IO device allows us to benchmark performance SuperGarbageSim simulates apps go execute instructions disassembly show disassembled instructions getmem print memory contents setmem set memory data setPC getPC Simulation Setup 4 Behavioral Simulation Correctly work at any cycle time constraint mif file Post route Simulation Setting a proper cycle time is important Modification of RAM contents needs a re creation of the module 5 Questions 6
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