Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6 002 Electronic Circuits Spring 2005 Problem Set 11 Solutions Introduction This homework assignment focuses on the analysis and design of a system for playing back a digitally stored audio signal Additionally this assignment serves as the pre lab exercises for Lab 4 which will involve the construction testing and demonstration of the audio playback system Consequently you should save a copy of your results for use during Lab 4 A block diagram of the audio playback system is shown in Figure 1 At the center of the system is a digital memory in which 32 768 samples of the audio signal are stored Each sample in the memory has a unique numerical address between 0 and 32 767 inclusive Consecutive samples are stored at consecutive addresses To obtain 32 768 consecutive samples of the audio signal 4 096 seconds of continuous analog audio signal are first sampled at an 8 kHz rate The analog audio samples are then digitized by an 8 bit analog to digital converter That is the samples are quantized to take on one of 256 possible discrete digital values between 0 and 255 inclusive Here the digital value of 0 corresponds to the most positive signal voltage and the digital value of 255 corresponds to the most negative signal voltage The resulting digital data is then written into the memory To retrieve the stored audio signal samples in sequence at the proper rate the memory is addressed by a counter which counts from 0 to 32 767 at an 8 kHz rate established by an external clock After counting to 32 767 the counter returns to 0 and the retrieval process repeats itself As the memory address increments the corresponding data appears at the memory output This data is converted back to an analog voltage in a piecewise constant manner by a digital to analog converter During the course of recording and playing back the analog audio signal the signal is sampled in time quantized in amplitude and reconstructed in a piecewise constant manner As you will learn in 6 003 this process introduces undesirable high frequency components into the signal To Speaker Clock Counter Memory D A Converter LowPass Filter Power Amp Figure 1 block diagram of the audio playback system minimize the perceived impact of these components the signal is filtered by a low pass filter after it is reconstructed by the digital to analog converter Finally the signal is amplified by a power amplifier which in turn drives a speaker In Lab 4 you will use a piezo electric speaker which does not require much power In this case the final power amplifier stage is not strictly necessary Nonetheless the stage is included here and is used to implement volume control In the course of this homework assignment you will analyze and design four of the functional blocks shown in Figure 1 These blocks are the clock the digital to analog converter the low pass filter and the power amplifier In Lab 4 you will construct these blocks and verify that they perform as desired Then you will combine them with the counter the read only memory and the speaker to construct and demonstrate the entire audio play back system Since you will construct the system from the components in your 6 002 lab kit your design of the blocks must account for the fact that the available components are limited Problem 1 The Clock The circuit shown in Figure 2 is the system clock which is a square wave oscillator followed by a CMOS inverter the inverter functions only as a negative gain buffer The oscillator is constructed from another CMOS inverter a resistor and a capacitor Both inverters are powered between the positive supply voltage VS and ground and both exhibit the hysteretic input output characteristic defined in the figure The inverters are otherwise ideal A Assume that vCAP has just charged up to VH so that vOSC has just switched to 0 V How much time elapses before vCAP decays to VL which in turn causes vOSC to switch to VS ANSWER As shown in the Figure 3 the capacitor voltage now begins to decay from VH towards 0 V In this case the capacitor voltage is given by vCAP VH e t RC where t 0 is the time at which vOSC just switches to 0 V We must now solve for the time R IN vCAP OUT C vOSC vCLK vOUT VS vIN VL Figure 2 the system clock VH VS VS vOSC VH vCAP VL 0 T1 T2 Figure 3 general clock waveforms Note that the vCAP curve is not drawn well It seems to show VCAP settling to vH and vL instead of vS and 0 V at which vCAP VL this time is denoted by T2 in Figure 3 Thus VL VH e T2 RC so that T2 RC ln VH VL B Assume that vCAP has just decayed to VL so that vOSC has just switched to VS How much time elapses before vCAP charges up to VH which in turn causes vOSC to switch to 0 V ANSWER Again as shown in Figure 3 the capacitor voltage now begins to rise from VL towards VS In this case the capacitor voltage is given by vCAP VS VL VS e t RC where t 0 is the time at which just switches to VS We must now solve for the time at which vCAP VH this time is denoted by T1 in the Figure 3 Thus VH VS VL VS e T1 RC so that VS VL T1 RC ln VS VH C Determine the frequency of the oscillator in terms of R C VL VH and VS ANSWER The period T of the oscillator is T T1 T2 RC ln VS VL VH VS VH VL The frequency f is the inverse of the period T and is given by f 1 1 V L VH T RC ln VSS V VH VL vCLK vOSC 5V 3V vCAP 1 8V t us 0V T2 64 8 us T1 59 6 us Figure 4 clock waveforms given the as designed component values Again note that the vCAP curve is not drawn well It seems to show VCAP settling to vH and vL instead of vS and 0 V D Assume that VL 1 8 V VH 3 0 V and VS 5 0 V Choose values for R and C so that the oscillator oscillates at or very near 8 kHz Since oscillator frequency alone under specifies R and C there is no single correct choice Therefore choose values for R and C that are easily implemented with the components in the 6 002 lab kit ANSWER A frequency of f 8 KHz is equivalent to T 1 f 125 s Pick C 0 0047 F and solve for R using the equation from Part C This yields R T C ln VS VL VH VS VH VL 27 K which is a standard resistor value E For the choice of R and C from Part D sketch and clearly label a …
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