Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6 002 Circuits Electronics Spring 2004 Problem Set 6 Issued 3 10 04 Due 3 17 04 Exercise 6 1 The ampli er shown below is constructed with a non quadratic MOSFET having the vDS iD characteristics shown below These characteristics are plotted for vGS 2 V 3 V 12 V and V For vGS 2 V the MOSFET is cut o Using graphical analysis plot the input output characteristic of the ampli er for 0 V vIN 10 V That is plot vOUT as a function of vIN Note the last page of this problem set contains a larger graph of the MOSFET characteristics It can be turned in with your problem set solutions MOSFET Characteristics 5 vGS 8 V 4 5 vGS 7 V 1 25 k v 6V v 5V GS 4 3 5 GS iD mA 3 10V vIN vGS 4 V vOUT 2 5 2 1 5 v GS 3V 1 0 5 vGS 2 V 0 0 1 2 3 4 5 v DS 6 7 8 9 10 V Exercise 6 2 Find the capacitance of the all capacitor network and the inductance of the all inductor network shown below C1 L2 L1 C2 C3 L3 Problem 6 1 This problem studies the propagation delay of digital signals through the inverter shown below Assume that the MOSFET in the inverter acts as a switch with on state resistance RON The inverter is loaded with a capacitor having capacitance CG that models the combined input capacitance of the logic gates connected to its output Assume that the inverter obeys the static discipline de ned in part by VOL and VOH A Assume that the MOSFET has been o for a very long time At t 0 vIN turns the MOSFET on Determine vG t for t 0 B How long does it take vG t to pass by VOL This delay is the fall time of the inverter C Assume that the MOSFET has been on for a very long time At t 0 vIN turns the MOSFET o Determine vG t for t 0 D How long does it take vG t to pass by VOH This delay is the rise time of the inverter E How can the fall and rise times be shortened via the design of RPU What limits the extent to which this design path may be followed RPU VS vIN CG vG Problem 6 2 In the circuit shown below a MOSFET and an external resistor having resistance RX are used to control the current iR in the winding of a relay Here the relay is modeled as a series inductor and resistor having inductance LR and resistance RR respectively The MOSFET may be modeled as an ideal switch A At t 0 vIN turns the MOSFET on so that vDS 0 Determine iR t for t 0 given that iR t 0 0 B Next at t T vIN turns the MOSFET o Determine both iR t and vDS t for t T Hint iR t is continuous at t T C Sketch and clearly label graphs of both iR t and vDS t for t 0 assuming that T 5LR RR and RX RR D The relay control circuit would be less expensive without the external resistor which may be removed from the circuit by considering the limit RX Why might such a cost reduction be unwise Relay VS vIN LR iR RX RR vDS Problem 6 3 At t 0 the networks shown below have zero initial state That is the capacitor voltage v t and the inductor current i t are both zero at t 0 At t 0 the voltage source produces an impulse of area and the current source produces an impulse of area Q A Derive the di erential equation that relates v t to I t and i t to V t Hint consider using Thevenin or Norton equivalent networks to simplify the work B Find the capacitor voltage v t and the inductor current i t at both t 0 and t One way to nd the states at t 0 is to integrate the corresponding di erential equations from t 0 to t 0 under the assumption that each state remains nite during that time you should justify this assumption Then substitute the initial conditions at t 0 into the results to determine the states at t 0 Try to determine the states at t through physical rather than mathematical reasoning C Next nd the time constant by which each state goes from its initial value at t 0 to its nal value at t D Using the previous results and without necessarily solving the di erential equations directly construct v t and i t for t 0 E Verify that the solutions to Part D are correct by substituting them into the di erential equation found in Part A i t R2 R1 I t C I t v t V t R1 L R2 V t Q t 0 t 0 Figure for Exercise 6 1 MOSFET Characteristics 5 v GS 8V 4 5 vGS 7 V v 6V v 5V GS 4 3 5 GS iD mA 3 2 5 vGS 4 V 2 1 5 v GS 3V 1 0 5 vGS 2 V 0 0 1 2 3 4 5 vDS V 6 7 8 9 10
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