Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6 002 Electronic Circuits Fall 2004 Lab 1 Thevenin Norton Equivalents Logic Gates Handout F04 018 Introduction The rst part of the lab explores the characterization of a network by its Thevenin and Norton equivalents The second part explores the static behavior of logic gates constructed with n channel MOSFETs and resistors You should complete the pre lab exercises in your lab notebook before coming to lab Then carry out the in lab exercises between September 27 and October 1 After completing the in lab exercises have a TA or LA check your work and sign your lab notebook Finally complete the post lab exercises in your lab notebook and turn in your lab notebook during recitation on Wednesday October 6 Pre Lab Exercises Pre Lab Exercises 1 1 and 1 2 explore the characterization of a network by its Thevenin and Norton equivalents Pre Lab Exercises 1 3 through 1 5 explore the static behavior of logic gates 1 1 Determine the Thevenin and Norton equivalents of the network shown in Figure 1 as viewed at its port V R1 R3 R2 Figure 1 source resistor network for Pre Lab Exercises 1 1 and 1 2 1 2 Evaluate the Thevenin and Norton equivalents of the network for the following values V 5 V R1 50 R2 2 2 k R3 1 5 k 1 3 Figure 2 shows a NOT gate a NOR gate and a NAND gate constructed from n channel MOSFETs and 1 k resistors The gure also shows a switch resistor model for the nchannel MOSFET Using the switch resistor model compute vOUT for all three gates In doing so consider all combinations of input voltages an input voltage may be either above or below the MOSFET threshold voltage VT In each case evaluate vOUT assuming RDS ON 4 Summarize your results for each gate in a table 1 4 Figure 3 shows a combinational logic circuit Determine the input output truth table for this circuit 1 5 Draw the circuit diagram for the combinational logic circuit shown in Figure 3 using the gates shown in Figure 2 NOT Gate 5V 1k 1k vOUT vIN vOUT vIN1 vIN2 MOSFET Model 5V NAND Gate D 1k vIN1 NOR Gate 5V vIN2 vOUT G Open vG S V T Closed vG S V T RDS ON S Figure 2 a NOT gate a NOR gate a NAND gate and the switch resistor MOSFET model IN1 IN2 IN3 OUT Figure 3 combinational logic circuit for Pre Lab Exercises 1 4 and 1 5 In Lab Exercises In Lab Exercises 1 1 through 1 3 explore the characterization of a network by its Thevenin and Norton equivalents In Lab exercises 1 4 through 1 9 explore the static behavior of logic gates 1 1 Construct the network shown in Figure 4 However before connecting the signal generator to the remainder of the network set its output voltage to a constant 5 V and check this output with the multi meter The network is the same as the one shown in Figure 1 with the function generator serving as both the voltage source and resistor R1 Note The function generator has two modes to compensate for the load impedance 50 and High Z Make sure that your function generator is set to the High Z mode Press Shift and then Enter to get to the menus Using the dial switch to menu D the SYS MENU Next press the down arrow twice Use the dial to switch to HIGH Z Then press Enter to save i 50 1 5k 2 2k v Signal Generator Figure 4 experimental source resistor network 1 2 Measure the open circuit voltage and short circuit current of the network with the multimeter Note that the multi meter is itself a near open circuit when used as a voltmeter and a near short circuit when used as an ammeter Therefore the direct connection of the multi meter across the port implements the proper measurement in both cases Your results from Pre Lab Exercise 1 2 should show that both measurements are within the safe range for the multi meter 1 3 Connect a resistor across the network port and measure the port voltage v with the multimeter Do so for resistors having resistances of 560 1 k and 2 2 k 1 4 Construct the circuit shown in Figure 5 which is designed to measure the threshold voltage of the MOSFET the MOSFET pin assignments are given in the attached data sheet The MOSFET should say 2N7000 on it Make sure that you don t accidentally reverse the polarity of the MOSFET The source should be connected to ground and the drain to the 1 k resistor As evident from the MOSFET schematic in the datasheet note that the drain and soure terminals of discrete MOSFETs are not symmetric Use the multi meter to measure vGS and the oscilloscope to measure vDS and set the signal generator to provide a constant output With vGS at 0 V vDS should be at 5 V Gradually increase vGS until vDS starts to fall The value of vGS at which this occurs is VT 1 5 Beginning with the circuit shown in Figure 5 remove the 1 k resistor and the oscilloscope from the MOSFET drain With vGS at 5 V measure RDS with the multi meter This resistance is RDS ON for vGS 5 V note that the multi meter supplies a very small voltage when used as an ohmmeter 1 6 Construct the NOT gate from Figure 2 and connect its input to a switch and 10 k resistor To Multimeter 5V Signal Generator 1k 50 V D To Oscilloscope G S Figure 5 circuit to measure VT as shown in Figure 6 For both switch positions that is for both logic input levels to the gate measure vOUT with the multi meter A switch pack and a 10 k resistor array 10k SIP pn A103J have been chosen to simplify the wiring of the switches to their associated resistors Speci cally the switch pack can be placed in the protoboard so that one side is on a common ground strip and each pin on the other side is on a separate trace Then the resistor array can be inserted into the protoboard along side the switch pack so that separate resistors connect to each switch Finally the common pin of the resistor pack designated by the white circle can be connected to the 5 V power supply through a single wire A diagram of this setup is seen in Figure 7 1 7 Construct the NOR gate from Figure 2 As for the NOT gate shown in Figure 6 connect the inputs to the NOR gate to switches and 10 k resistors For all combinations of switch positions that is for all combinations of logic input levels to the gate measure vOUT with the multi meter Save the NOR gate for In Lab Exercise 1 9 1 8 Repeat In Lab Exercise 1 7 for the NAND gate Save the NAND gate for In Lab …
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