Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6 002 Circuits Electronics Spring 2004 Problem Set 3 Issued 2 18 04 Due 2 27 04 Exercise 3 1 A battery is measured to have an open circuit voltage of 1 5 V It can deliver 2 5 A to a 0 5 resistor How much current can it deliver to a short circuit Hint consider the Norton equivalent of the battery Exercise 3 2 This exercise applies two di erent analyses to determine the unknown node voltages in Network A shown below It illustrates that the direct method of analysis is not always the simplest A Using nodal analysis nd the unknown node voltages in Network A Hint see Problem 1 3 B First explain why Network A may be re drawn as Network B Second combine the lefthand source with the two left most resistors to form their Thevenin equivalent and redraw the resulting network Third combine the right hand source with the two right most resistors to form their Thevenin equivalent and again redraw the resulting network Finally using superposition determine the two unknown node voltages in the thrice re drawn version of Network A thereby completing the analysis Your answers to Parts A and B should be the same 3R R V 3R R R Network A R V 3R R R V 3R Network B Exercise 3 3 A Norton equivalent network is used to excite a nonlinear resistor as shown below The graphical i v characteristic that de nes the nonlinear resistor is also shown below Determine the terminal current iNR and the terminal voltage vNR of the nonlinear resistor for all values of IN Hint consider using a load line analysis to gain insight iNR IN iNR Nonlinear Resistor RN GNR vNR vNR VNR Problem 3 1 Consider the Boolean logic bu er having the real input output characteristic shown below The dashed diagonal is for referene The usual static discipline is to be de ned for this bu er such that VOL VIL VIH VOH The high level noise margin for this static discipline is VOH VIH The low level noise margin for this static discipline is VIL VOL A If zero noise margin were acceptable over what voltage range could VIL be chosen What is the corresponding voltage range of VOL B What combination of VIL and VOL maximizes the low level noise margin C If zero noise margin were acceptable over what voltage range could VIH be chosen What is the corresponding voltage range of VOH D What combination of VIH and VOH maximizes the high level noise margin 1 OUTPUT VOLTAGE V 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 1 0 2 0 3 0 4 0 5 0 6 INPUT VOLTAGE 0 7 V 0 8 0 9 1 Problem 3 2 This problem shows that there is often more than one way in which to implement a particular Boolean logic function and that the most direct way is not always the simplest Here the two input exclusive or XOR gate serves as an example The Boolean logic function that this gate implements is OUT IN1 IN2 IN1 IN2 Thus its output is true if one or the other input is true but not both A Using AND gate OR gate and NOT gate inverter Boolean logic symbols implement a twoinput XOR gate by directly implementing the Boolean logic function that de ned it above B Design an NMOS inverter an NMOS two input AND gate and an NMOS two input OR gate using a minimum of MOSFETs and pull up resistors C Combine your results from Parts A and B to implement an NMOS two input XOR gate Your implementation should require eleven MOSFETs and eight pull up resistors D Using truth tables prove DeMorgan s law DeMorgan s Law states that A B A B or equivalently that A B A B or equivalently that A B A B or equivalently that A B A B Note that the second version of DeMorgan s Law can be derived by inverting the rst version and that the third and fourth versions can be derived from the second and rst versions respectively by substituting A for A and B for B E Using only inverters and two input NOR gates implement an alternative NMOS two input XOR gate This can be done with as few as nine MOSFETs and six pull up resistors Hint use DeMorgan s Law to modify your result found in Part A Problem 3 3 Consider the NMOS two input OR gate shown below This gate is to be implemented with MOSFETs having 1 V VT 4 V and 103 RON 106 and pull up resistors having 103 RPU 106 The inequalities express a permissible design space as opposed to a range of manufacturing uncertainty The MOSFETs and pull up resistors need not have identical parameters Complete the design of the OR gate by choosing values for each VT RON and RPU so that VOL 1 V VIL 2 V VIH 3 V VOH 4 V and the power dissipated by the gate is minimized If any parameter does not have a unique design value then give the permissible range for that parameter Assume VS 5V VS RPU1 RPU2 M3 M1 VIN1 VIN2 M2 VOUT Problem 3 4 The switch resistor SR model of a MOSFET is a highly simpli ed model that is nonetheless very useful for describing the behavior of a MOSFET in a digital logic circuit However this model is so simpli ed that it can lead to inconsistent analyses in some cases as illustrated by this problem Consider the analysis of the two input NAND and two input NOR gates shown below Assume that all MOSFETS in these gates behave according to the SR model with a threshold voltage VT 1 V and on state resistance RON Further let RPU RON and VS 3 V A Consider the two input NAND gate Let VIN1 VIN2 1 5 V Assume that M2 is on and determine vOUT and vGS for M2 Is M1 on or o Is the value of vGS consistent with the assumption that M2 is on B Again consider the two input NAND gate and again let VIN1 VIN2 1 5 V Now assume that M2 is o and determine vOUT and vGS for M2 Is the value of vGS consistent with the assumption that M2 is o C From your answers to Parts A and B you should conclude that M2 can be neither on nor o What characteristics of the SR model and the design of the two input NAND gate allow this inconsistency to occur How do you think the real circuit actually behaves D How high must VIH be de ned for the two input NAND gate so that the inconsistent analysis found above is inconsequential to the proper operation of the gate E Consider now the two input NOR gate Can its analysis produce the same inconsistency for any combination of parameter values Why or why not …
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