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Table 18.1 Cache Latency (in clock cycles) CPU Clock Frequency L1 Cache L2 Cache L3 Cache Core 2 Quad 2.66 GHz 3 cycles 15 cycles — Core i7 2.66 GHz 4 cycles 11 cycles 39 cyclesTable 18.2 ARM11 MPCore Configurable Options Feature Range of options Default value Processors 1 to 4 4 Instruction cache size per processor 16 KB, 32 KB, or 64 KB 32 KB Data cache size per processor 16 KB, 32 KB, or 64 KB 32 KB Master ports 1 or 2 2 Width of interrupt bus 0 to 224 by increments of 32 pins 32 pins Vector floating point (VFP) coprocessor per processor Included or not
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