Internal Memory Core Memory Semiconductor Memory - memory cell - RAM Memory o wired-in addressing logic – are used to access individual words o rapid reading & writing is possible o volatile – constant power supply required o temporary storage - ROM/PROM Memory – (read only, programmable read-only) o read-only o non-volatile o permanent storage - EPROM Memory (erasable & programmable) o mostly read-only o erasable & writable via UV light source (off-line) o non-volatile o permanent storage - EEPROM Memory (electronically erasable & programmable) o mostly read-only o electronically erasable & writable (on-line) o non-volatile o permanent storage - Flash Drive Memory o block-level read & write – slow (storage device) o mixed features of both main memory & disk storage o electronically erasable & writable (on-line) o non-volatile o permanent storage Memory Cell Control Signal Read/Write Select (activate cell) Sense Data Flow Out Data Flow In Data Flow consists of a single bit, i.e., zero or one each core held one bit core external diameter: 1/8, 1/16, 1/32 inch Semiconductor Memory Cell Properties - two stable (semi-stable) states - capable of being written at least once - capable of being read to sense the stateRAM Memory -- used for Main Memory DRAM – dynamic RAM - DRAM cells store a charge on a capacitor o presence of a charge indicates 1 o absence of a charge indicates 0 - capacitors have a natural tendency to discharge  require periodic recharging - tendency of the stored charge to leak away  dynamic - analog device, i.e., Sense Amplifier measures the Storage Capacitors contents Output Value transistor DRAM Address Line Storage Capacitor Ground Bit Line B Transistor acts as a switch - if address line is charged it allows current to flow between the capacitor and bit line B - if address line is not charged it blocks the flow of current between the capacitor and the bit line B holds one bit Write Operation 1. Voltage signal is applied to the bit line - High voltage == 1 - Low voltage == 0 2. Signal is applied to the address line allowing the charge to be transferred to the capacitor Read Operation 1. Signal is applied to the address line allowing the charge on the capacitor to be released via the bit line to a sense amplifier 2. Sense amplifier compares the capacitor voltage to a reference value and determines whether the cell contains a zero (0) or a one (1) 3. Since the capacitor is now discharged, it must be rewritten to complete the operation DRAM cells are ANALOG DEVICES since they use a capacitor to hold a voltage charge which must be MEASURED to determine whether it represents a zero or a one, i.e., the capacitor may hold any charge value within a specified range Sense Amplifier with a Reference Value Input ValueSRAM – static RAM – used for Cache Memory - digital device - flip-flop logic-gate - holds data as long as power supply exists - no refresh is required to hold data DRAM versus SRAM - DRAM cells – main memory o are simpler & smaller than SRAM cells o can be more can be tightly packed together than SRAM cells o inexpensive o require refresh circuitry - SRAM -- cache memory o faster than DRAM – do not require rewriting upon reading ROM Memory T1 transistor T5 transistor Ground Address Line Bit Line B T4 transistor T3 transistor T6 transistor T2 transistor Bit Line B--- dc voltage C1 C2 Logic State 1 point C1 – high T1 & T4 off point C2 – low T2 & T3 on Logic State 0 point C1 – low T1 & T4 on point C2 – high T2 & T3 off SRAM address line is used to open/close the transistor switches T5 & T6 which allows a read/write operation Write Operation - desired bit value is supplied to bit line B and the complement value is supplied to bit line B---- - the four transistors T1, T2, T3, T4 are forced into proper state to hold the desired bit value Read Operation - bit value is read from bit line BUsage: - microprogramming - library subroutines - system programs - function tables PROM Memory – programmable ROM Write-Mostly Memory - EPROM – erasable programmable ROM http://en.wikipedia.org/wiki/EPROM o optical media o all storage cells on the chip are erased to an initial state by exposure to an intense ultra-violet light o erasure may be done repeatedly o erasure may take 10-20 minutes to perform o one transistor per cell o more expensive than PROM - EEPROM – electronically erasable programmable ROM http://en.wikipedia.org/wiki/EEPROM o rewritable at the byte level without prior erasure o writable in place, i.e., on-line, using ordinary bus control, address & data lines o field-effect transistors http://en.wikipedia.org/wiki/Field_effect_transistor o write operation takes several hundred microseconds per byte, i.e., 0.5 – 0.01 milliseconds o completion time: read operation write operation o more expensive than EPROM o less dense than EPROM - Flash Memory o rewritable at the block level without prior erasure o one transistor per cell o entire blocks of memory cells are erased in a single flash o erasure of entire flash memory can be accomplished in a few seconds Chip Organization & Functional Logic - data is permanently in main memory, i.e., read-only - program permanently in main memory - nonvolatile - no power source required - information is “burned”, i.e., “hard-wired” into chip during fabrication - chip creation must be exact – an error in a single bit invalidates the entire chip run - high-volume production runs - data is permanently in main memory, i.e., read-only after write-once - program permanently in main memory - nonvolatile - no power source required - information is electronically inserted into the chip after fabrication using special equipment while the chip is off-line - low or medium volume production runs Flash memory is not byte addressable- Organizational Principle -- number of bits of data read/written at a time o Physical arrangement of cells in the array is the same as the logical arrangement of words in memory, i.e., array contains W words of B bits each, e.g., 16-Mbit chip organized as 1M of 16 bit words o One