Table 8.1 Sample Program Execution Attributes JOB1 JOB2 JOB3 Type of job Heavy compute Heavy I/O Heavy I/O Duration 5 min 15 min 10 min Memory required 50 M 100 M 80 M Need disk? No No Yes Need terminal? No Yes No Need printer? No No YesTable 8.2 Effects of Multiprogramming on Resource Utilization Uniprogramming Multiprogramming Processor use 20% 40% Memory use 33% 67% Disk use 33% 67% Printer use 33% 67% Elapsed time 30 min 15 min Throughput rate 6 jobs/hr 12 jobs/hr Mean response time 18 min 10 minTable 8.3 Batch Multiprogramming versus Time Sharing Batch Multiprogramming Time Sharing Principal objective Maximize processor use Minimize response time Source of directives to operating system Job control language commands provided with the job Commands entered at the terminalTable 8.4 Types of Scheduling Long-term scheduling The decision to add to the pool of processes to be executed Medium-term scheduling The decision to add to the number of processes that are partially or fully in main memory Short-term scheduling The decision as to which available process will be executed by the processor I/O scheduling The decision as to which process's pending I/O request shall be handled by an available I/O deviceTable 8.5 Pentium II Memory Management Parameters (page 1 of 2) Segment Descriptor (Segment Table Entry) Base Defines the starting address of the segment within the 4-GByte linear address space. D/B bit In a code segment, this is the D bit and indicates whether operands and addressing modes are 16 or 32 bits. Descriptor Privilege Level (DPL) Specifies the privilege level of the segment referred to by this segment descriptor. Granularity bit (G) Indicates whether the Limit field is to be interpreted in units by one byte or 4 KBytes. Limit Defines the size of the segment. The processor interprets the limit field in one of two ways, depending on the granularity bit: in units of one byte, up to a segment size limit of 1 MByte, or in units of 4 KBytes, up to a segment size limit of 4 GBytes. S bit Determines whether a given segment is a system segment or a code or data segment. Segment Present bit (P) Used for nonpaged systems. It indicates whether the segment is present in main memory. For paged systems, this bit is always set to 1. Type Distinguishes between various kinds of segments and indicates the access attributes.Table 8.5 Pentium II Memory Management Parameters (page 2 of 2) Page Directory Entry and Page Table Entry Accessed bit (A) This bit is set to 1 by the processor in both levels of page tables when a read or write operation to the corresponding page occurs. Dirty bit (D) This bit is set to 1 by the processor when a write operation to the corresponding page occurs. Page Frame Address Provides the physical address of the page in memory if the present bit is set. Since page frames are aligned on 4K boundaries, the bottom 12 bits are 0, and only the top 20 bits are included in the entry. In a page directory, the address is that of a page table. Page Cache Disable bit (PCD) Indicates whether data from page may be cached. Page Size bit (PS) Indicates whether page size is 4 KByte or 4 MByte. Page Write Through bit (PWT) Indicates whether write-through or write-back caching policy will be used for data in the corresponding page. Present bit (P) Indicates whether the page table or page is in main memory. Read/Write bit (RW) For user-level pages, indicates whether the page is read-only access or read/write access for user-level programs. User/Supervisor bit (US) Indicates whether the page is available only to the operating system (supervisor level) or is available to both operating system and applications (user level).Table 8.6 ARM Memory-Management Parameters Access Permission (AP), Access Permission Extension (APX) These bits control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, a Permission Fault is raised. Bufferable (B) bit Determines, with the TEX bits, how the write buffer is used for cacheable memory. Cacheable (C) bit Determines whether this memory region can be mapped through the cache. Domain Collection of memory regions. Access control can be applied on the basis of domain. not Global (nG) Determines whether the translation should be marked as global (0), or process specific (1). Shared (S) Determines whether the translation is for not-shared (0), or shared (1) memory. SBZ Should be zero. Type Extension (TEX) These bits, together with the B and C bits, control accesses to the caches, how the write buffer is used, and if the memory region is shareable and therefore must be kept coherent. Execute Never (XN) Determines whether the region is executable (0) or not executable
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