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CSUN COMP 546 - Internal Memory

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William Stallings Computer Organization and Architecture 8th EditionSemiconductor Memory TypesSemiconductor MemoryMemory Cell OperationDynamic RAMDynamic RAM StructureDRAM OperationStatic RAMStating RAM StructureStatic RAM OperationSRAM v DRAMRead Only Memory (ROM)Types of ROMOrganisation in detailRefreshingTypical 16 Mb DRAM (4M x 4)Packaging256kByte Module Organisation1MByte Module OrganisationInterleaved MemoryError CorrectionError Correcting Code FunctionAdvanced DRAM OrganizationSynchronous DRAM (SDRAM)SDRAMSDRAM Read TimingRAMBUSRAMBUS DiagramDDR SDRAMDDR SDRAM Read TimingSimplified DRAM Read TimingCache DRAMReadingWilliam Stallings Computer Organization and Architecture8th EditionChapter 5Internal MemorySemiconductor Memory TypesMemory Type Category Erasure Write Mechanism VolatilityRandom-access memory (RAM)Read-write memory Electrically, byte-level Electrically VolatileRead-only memory (ROM)Read-only memory Not possibleMasksNonvolatileProgrammable ROM (PROM)ElectricallyErasable PROM (EPROM)Read-mostly memoryUV light, chip-levelElectrically Erasable PROM (EEPROM)Electrically, byte-levelFlash memory Electrically, block-levelSemiconductor Memory•RAM —Misnamed as all semiconductor memory is random access—Read/Write—Volatile—Temporary storage—Static or dynamicMemory Cell OperationDynamic RAM•Bits stored as charge in capacitors•Charges leak•Need refreshing even when powered•Simpler construction•Smaller per bit•Less expensive•Need refresh circuits•Slower•Main memory•Essentially analogue—Level of charge determines valueDynamic RAM StructureDRAM Operation•Address line active when bit read or written—Transistor switch closed (current flows)•Write—Voltage to bit line–High for 1 low for 0—Then signal address line–Transfers charge to capacitor•Read—Address line selected–transistor turns on—Charge from capacitor fed via bit line to sense amplifier–Compares with reference value to determine 0 or 1—Capacitor charge must be restoredStatic RAM•Bits stored as on/off switches•No charges to leak•No refreshing needed when powered•More complex construction•Larger per bit•More expensive•Does not need refresh circuits•Faster•Cache•Digital—Uses flip-flopsStating RAM StructureStatic RAM Operation•Transistor arrangement gives stable logic state•State 1—C1 high, C2 low—T1 T4 off, T2 T3 on•State 0—C2 high, C1 low—T2 T3 off, T1 T4 on•Address line transistors T5 T6 is switch•Write – apply value to B & compliment to B•Read – value is on line BSRAM v DRAM•Both volatile—Power needed to preserve data•Dynamic cell —Simpler to build, smaller—More dense—Less expensive—Needs refresh—Larger memory units•Static—Faster—CacheRead Only Memory (ROM)•Permanent storage—Nonvolatile•Microprogramming (see later)•Library subroutines•Systems programs (BIOS)•Function tablesTypes of ROM•Written during manufacture—Very expensive for small runs•Programmable (once)—PROM—Needs special equipment to program•Read “mostly”—Erasable Programmable (EPROM)–Erased by UV—Electrically Erasable (EEPROM)–Takes much longer to write than read—Flash memory–Erase whole memory electricallyOrganisation in detail•A 16Mbit chip can be organised as 1M of 16 bit words•A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on•A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array—Reduces number of address pins–Multiplex row address and column address–11 pins to address (211=2048)–Adding one more pin doubles range of values so x4 capacityRefreshing•Refresh circuit included on chip•Disable chip•Count through rows•Read & Write back•Takes time•Slows down apparent performanceTypical 16 Mb DRAM (4M x 4)Packaging256kByte Module Organisation1MByte Module OrganisationInterleaved Memory•Collection of DRAM chips•Grouped into memory bank•Banks independently service read or write requests•K banks can service k requests simultaneouslyError Correction•Hard Failure—Permanent defect•Soft Error—Random, non-destructive—No permanent damage to memory•Detected using Hamming error correcting codeError Correcting Code FunctionAdvanced DRAM Organization•Basic DRAM same since first RAM chips•Enhanced DRAM—Contains small SRAM as well—SRAM holds last line read (c.f. Cache!)•Cache DRAM—Larger SRAM component—Use as cache or serial bufferSynchronous DRAM (SDRAM)•Access is synchronized with an external clock•Address is presented to RAM•RAM finds data (CPU waits in conventional DRAM)•Since SDRAM moves data in time with system clock, CPU knows when data will be ready•CPU does not have to wait, it can do something else•Burst mode allows SDRAM to set up stream of data and fire it out in block•DDR-SDRAM sends data twice per clock cycle (leading & trailing edge)SDRAMSDRAM Read TimingRAMBUS•Adopted by Intel for Pentium & Itanium•Main competitor to SDRAM•Vertical package – all pins on one side•Data exchange over 28 wires < cm long•Bus addresses up to 320 RDRAM chips at 1.6Gbps•Asynchronous block protocol—480ns access time—Then 1.6 GbpsRAMBUS DiagramDDR SDRAM•SDRAM can only send data once per clock•Double-data-rate SDRAM can send data twice per clock cycle—Rising edge and falling edgeDDR SDRAM Read TimingSimplified DRAM Read TimingCache DRAM•Mitsubishi•Integrates small SRAM cache (16 kb) onto generic DRAM chip•Used as true cache—64-bit lines—Effective for ordinary random access•To support serial access of block of data—E.g. refresh bit-mapped screen–CDRAM can prefetch data from DRAM into SRAM buffer–Subsequent accesses solely to SRAMReading•The RAM


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CSUN COMP 546 - Internal Memory

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