Internal MemoryCore MemorySemiconductor Memory- memory cell- RAM Memoryo wired-in addressing logic – are used to access individual words o rapid reading & writing is possibleo volatile – constant power supply requiredo temporary storage- ROM/PROM Memory – (read only, programmable read-only)o read-onlyo non-volatile o permanent storage- EPROM Memory (erasable & programmable)o mostly read-onlyo erasable & writable via UV light source (off-line)o non-volatile o permanent storage- EEPROM Memory (electronically erasable & programmable)o mostly read-onlyo electronically erasable & writable (on-line)o non-volatile o permanent storage- Flash Drive Memoryo block-level read & write – slow (storage device) o mixed features of both main memory & disk storageo electronically erasable & writable (on-line)o non-volatile o permanent storageMemory CellControl SignalRead/WriteSelect(activate cell)Sense Data Flow OutData Flow InData Flow consists ofa single bit, i.e., zeroor oneeach core held one bitcore external diameter: 1/8, 1/16, 1/32 inchSemiconductor Memory Cell Properties- two stable (semi-stable) states- capable of being written at least once- capable of being read to sense the stateRAM Memory -- used for Main MemoryDRAM – dynamic RAM- DRAM cells store a charge on a capacitoro presence of a charge indicates 1o absence of a charge indicates 0 - capacitors have a natural tendency to discharge  require periodic recharging- tendency of the stored charge to leak away  dynamic - analog device, i.e., Sense Amplifier measures the Storage Capacitors contentsOutput ValuetransistorDRAM Address LineStorage CapacitorGroundBit Line BTransistor acts as a switch - if address line is charged it allows current to flow between the capacitor and bit line B - if address line is not charged it blocks the flow of current between the capacitor and the bit line B holds one bitWrite Operation1. Voltage signal is applied to the bit line- High voltage == 1- Low voltage == 02. Signal is applied to the address line allowing the charge to be transferred to the capacitor Read Operation1. Signal is applied to the address line allowing the charge on the capacitor to be released via the bit line to a sense amplifier2. Sense amplifier compares the capacitor voltage to a reference value and determines whether the cell contains a zero (0) or a one (1)3. Since the capacitor is now discharged, it must be rewritten to complete the operationDRAM cells are ANALOG DEVICESsincethey use a capacitor to hold a voltage charge which must be MEASURED to determine whether it represents a zero or a one, i.e., the capacitor mayhold any charge value within a specified rangeSense Amplifierwith aReference ValueInput ValueSRAM – static RAM – used for Cache Memory- digital device- flip-flop logic-gate- holds data as long as power supply exists- no refresh is required to hold dataDRAM versus SRAM- DRAM cells – main memoryo are simpler & smaller than SRAM cellso can be more can be tightly packed together than SRAM cellso inexpensiveo require refresh circuitry - SRAM -- cache memoryo faster than DRAM – do not require rewriting upon readingROM MemoryT1 transistorT5 transistorGroundAddress LineBit Line BT4 transistorT3 transistorT6 transistorT2 transistorBit Line B---dc voltageC1C2Logic State 1point C1 – high T1 & T4 off point C2 – low T2 & T3 on Logic State 0point C1 – low T1 & T4 on point C2 – high T2 & T3 off SRAM address line is used to open/close the transistor switches T5 &T6 which allows a read/write operationWrite Operation-desired bit value is supplied to bit line B and the complement value is supplied to bit line B-----the four transistors T1, T2, T3, T4 are forced into proper state to hold the desired bit valueRead Operation- bit value is read from bit line BUsage:- microprogramming- library subroutines- system programs- function tablesPROM Memory – programmable ROMWrite-Mostly Memory- EPROM – erasable programmable ROM http://en.wikipedia.org/wiki/EPROMo optical mediao all storage cells on the chip are erased to an initial state by exposure to an intense ultra-violet lighto erasure may be done repeatedlyo erasure may take 10-20 minutes to performo one transistor per cello more expensive than PROM - EEPROM – electronically erasable programmable ROM http://en.wikipedia.org/wiki/EEPROMo rewritable at the byte level without prior erasureo writable in place, i.e., on-line, using ordinary bus control, address & data lineso field-effect transistors http://en.wikipedia.org/wiki/Field_effect_transistoro write operation takes several hundred microseconds per byte, i.e., 0.5 – 0.01 millisecondso completion time: read operation write operationo more expensive than EPROMo less dense than EPROM- Flash Memoryo rewritable at the block level without prior erasureo one transistor per cello entire blocks of memory cells are erased in a single flasho erasure of entire flash memory can be accomplished in a few seconds- data is permanently in main memory, i.e., read-only- program permanently in main memory- nonvolatile- no power source required- information is “burned”, i.e., “hard-wired” into chip during fabrication- chip creation must be exact – an error in a single bit invalidates the entire chip run- high-volume production runs- data is permanently in main memory, i.e., read-only after write-once- program permanently in main memory- nonvolatile- no power source required- information is electronically inserted into the chip after fabrication using special equipment while the chip is off-line- low or medium volume production runsFlash memory is not byte addressableChip Organization & Functional Logic- Organizational Principle -- number of bits of data read/written at a timeo Physical arrangement of cells in the array is the same as the logical arrangement of words in memory, i.e., array contains W words of B bits each, e.g., 16-Mbit chip organized as 1M of 16 bit wordso One bit per chip arrangement, data is written 1 bit at a timeRow Address Select Column Address Select Write Enable Output Enable 4 bits are read or written at a time row line connects to the Select terminal of each cell in the row column line connects to the Data-In/Sense terminal of each cell in the column eleven address lines, e.g., A0, A1, …, A10 supply the address of the data item selected decoder activates a single output line depending on the