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CSUN COMP 546 - Top Level View of Computer Function and Interconnection

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William Stallings Computer Organization and Architecture 8th EditionProgram ConceptWhat is a program?Function of Control UnitComponentsComputer Components: Top Level ViewInstruction CycleFetch CycleExecute CycleExample of Program ExecutionInstruction Cycle State DiagramInterruptsProgram Flow ControlInterrupt CycleTransfer of Control via InterruptsInstruction Cycle with InterruptsProgram Timing Short I/O WaitProgram Timing Long I/O WaitInstruction Cycle (with Interrupts) - State DiagramMultiple InterruptsMultiple Interrupts - SequentialMultiple Interrupts – NestedTime Sequence of Multiple InterruptsConnectingComputer ModulesMemory ConnectionInput/Output Connection(1)Input/Output Connection(2)CPU ConnectionBusesWhat is a Bus?Data BusAddress busControl BusBus Interconnection SchemeBig and Yellow?Physical Realization of Bus ArchitectureSingle Bus ProblemsTraditional (ISA) (with cache)High Performance BusBus TypesBus ArbitrationCentralised or Distributed ArbitrationTimingSynchronous Timing DiagramAsynchronous Timing – Read DiagramAsynchronous Timing – Write DiagramPCI BusPCI Bus Lines (required)PCI Bus Lines (Optional)PCI CommandsPCI Read Timing DiagramPCI Bus ArbiterPCI Bus ArbitrationForeground ReadingWilliam Stallings Computer Organization and Architecture8th EditionChapter 3Top Level View of Computer Function and InterconnectionProgram Concept•Hardwired systems are inflexible•General purpose hardware can do different tasks, given correct control signals•Instead of re-wiring, supply a new set of control signalsWhat is a program?•A sequence of steps•For each step, an arithmetic or logical operation is done•For each operation, a different set of control signals is neededFunction of Control Unit•For each operation a unique code is provided—e.g. ADD, MOVE•A hardware segment accepts the code and issues the control signals•We have a computer!Components•The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit•Data and instructions need to get into the system and results out—Input/output•Temporary storage of code and results is needed—Main memoryComputer Components:Top Level ViewInstruction Cycle•Two steps:—Fetch—ExecuteFetch Cycle•Program Counter (PC) holds address of next instruction to fetch•Processor fetches instruction from memory location pointed to by PC•Increment PC—Unless told otherwise•Instruction loaded into Instruction Register (IR)•Processor interprets instruction and performs required actionsExecute Cycle•Processor-memory—data transfer between CPU and main memory•Processor I/O—Data transfer between CPU and I/O module•Data processing—Some arithmetic or logical operation on data•Control—Alteration of sequence of operations—e.g. jump•Combination of aboveExample of Program ExecutionInstruction Cycle State DiagramInterrupts•Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing•Program—e.g. overflow, division by zero•Timer—Generated by internal processor timer—Used in pre-emptive multi-tasking•I/O—from I/O controller•Hardware failure—e.g. memory parity errorProgram Flow ControlInterrupt Cycle•Added to instruction cycle•Processor checks for interrupt—Indicated by an interrupt signal•If no interrupt, fetch next instruction•If interrupt pending:—Suspend execution of current program —Save context—Set PC to start address of interrupt handler routine—Process interrupt—Restore context and continue interrupted programTransfer of Control via InterruptsInstruction Cycle with InterruptsProgram TimingShort I/O WaitProgram TimingLong I/O WaitInstruction Cycle (with Interrupts) - State DiagramMultiple Interrupts•Disable interrupts—Processor will ignore further interrupts whilst processing one interrupt—Interrupts remain pending and are checked after first interrupt has been processed—Interrupts handled in sequence as they occur•Define priorities—Low priority interrupts can be interrupted by higher priority interrupts—When higher priority interrupt has been processed, processor returns to previous interruptMultiple Interrupts - SequentialMultiple Interrupts – NestedTime Sequence of Multiple InterruptsConnecting•All the units must be connected•Different type of connection for different type of unit—Memory—Input/Output—CPUComputer ModulesMemory Connection•Receives and sends data•Receives addresses (of locations)•Receives control signals —Read—Write—TimingInput/Output Connection(1)•Similar to memory from computer’s viewpoint•Output—Receive data from computer—Send data to peripheral•Input—Receive data from peripheral—Send data to computerInput/Output Connection(2)•Receive control signals from computer•Send control signals to peripherals—e.g. spin disk•Receive addresses from computer—e.g. port number to identify peripheral•Send interrupt signals (control)CPU Connection•Reads instruction and data•Writes out data (after processing)•Sends control signals to other units•Receives (& acts on) interruptsBuses•There are a number of possible interconnection systems•Single and multiple BUS structures are most common•e.g. Control/Address/Data bus (PC)•e.g. Unibus (DEC-PDP)What is a Bus?•A communication pathway connecting two or more devices•Usually broadcast •Often grouped—A number of channels in one bus—e.g. 32 bit data bus is 32 separate single bit channels•Power lines may not be shownData Bus•Carries data—Remember that there is no difference between “data” and “instruction” at this level•Width is a key determinant of performance—8, 16, 32, 64 bitAddress bus•Identify the source or destination of data•e.g. CPU needs to read an instruction (data) from a given location in memory•Bus width determines maximum memory capacity of system—e.g. 8080 has 16 bit address bus giving 64k address spaceControl Bus•Control and timing information—Memory read/write signal—Interrupt request—Clock signalsBus Interconnection SchemeBig and Yellow?•What do buses look like?—Parallel lines on circuit boards—Ribbon cables—Strip connectors on mother boards–e.g. PCI—Sets of wiresPhysical Realization of Bus ArchitectureSingle Bus Problems•Lots of devices on one bus leads to:—Propagation delays–Long data paths mean that co-ordination of bus use can adversely affect performance–If aggregate data transfer approaches bus


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