William Stallings Computer Organization and Architecture 8th EditionWhat is an Instruction Set?Elements of an InstructionWhere have all the Operands Gone?Instruction Cycle State DiagramInstruction RepresentationSimple Instruction FormatInstruction TypesNumber of Addresses (a)Number of Addresses (b)Number of Addresses (c)Number of Addresses (d)How Many AddressesDesign Decisions (1)Design Decisions (2)Types of Operandx86 Data TypesSMID Data Typesx86 Numeric Data FormatsARM Data TypesARM Endian SupportTypes of OperationData TransferArithmeticShift and Rotate OperationsLogicalConversionInput/OutputSystems ControlTransfer of ControlBranch InstructionNested Procedure CallsUse of StackStack Frame Growth Using Sample Procedures P and QExercise For ReaderByte Order (A portion of chips?)Byte Order (example)Byte Order NamesExample of C Data StructureAlternative View of Memory MapStandard…What Standard?William Stallings Computer Organization and Architecture8th EditionChapter 10Instruction Sets:Characteristics and FunctionsWhat is an Instruction Set?•The complete collection of instructions that are understood by a CPU•Machine Code•Binary•Usually represented by assembly codesElements of an Instruction•Operation code (Op code)—Do this•Source Operand reference—To this•Result Operand reference—Put the answer here•Next Instruction Reference—When you have done that, do this...Where have all the Operands Gone?•Long time passing….•(If you don’t understand, you’re too young!)•Main memory (or virtual memory or cache)•CPU register•I/O deviceInstruction Cycle State DiagramInstruction Representation•In machine code each instruction has a unique bit pattern•For human consumption (well, programmers anyway) a symbolic representation is used—e.g. ADD, SUB, LOAD•Operands can also be represented in this way—ADD A,BSimple Instruction FormatInstruction Types•Data processing•Data storage (main memory)•Data movement (I/O)•Program flow controlNumber of Addresses (a)•3 addresses—Operand 1, Operand 2, Result—a = b + c;—May be a forth - next instruction (usually implicit)—Not common—Needs very long words to hold everythingNumber of Addresses (b)•2 addresses—One address doubles as operand and result—a = a + b—Reduces length of instruction—Requires some extra work–Temporary storage to hold some resultsNumber of Addresses (c)•1 address—Implicit second address—Usually a register (accumulator)—Common on early machinesNumber of Addresses (d)•0 (zero) addresses—All addresses implicit—Uses a stack—e.g. push a— push b— add— pop c—c = a + bHow Many Addresses•More addresses—More complex (powerful?) instructions—More registers–Inter-register operations are quicker—Fewer instructions per program•Fewer addresses—Less complex (powerful?) instructions—More instructions per program—Faster fetch/execution of instructionsDesign Decisions (1)•Operation repertoire—How many ops?—What can they do?—How complex are they?•Data types•Instruction formats—Length of op code field—Number of addressesDesign Decisions (2)•Registers—Number of CPU registers available—Which operations can be performed on which registers?•Addressing modes (later…)•RISC v CISCTypes of Operand•Addresses•Numbers—Integer/floating point•Characters—ASCII etc.•Logical Data—Bits or flags•(Aside: Is there any difference between numbers and characters? Ask a C programmer!)x86 Data Types•8 bit Byte•16 bit word•32 bit double word•64 bit quad word•128 bit double quadword•Addressing is by 8 bit unit•Words do not need to align at even-numbered address•Data accessed across 32 bit bus in units of double word read at addresses divisible by 4•Little endianSMID Data Types•Integer types—Interpreted as bit field or integer•Packed byte and packed byte integer—Bytes packed into 64-bit quadword or 128-bit double quadword•Packed word and packed word integer—16-bit words packed into 64-bit quadword or 128-bit double quadword•Packed doubleword and packed doubleword integer—32-bit doublewords packed into 64-bit quadword or 128-bit double quadword•Packed quadword and packed qaudword integer—Two 64-bit quadwords packed into 128-bit double quadword •Packed single-precision floating-point and packed double-precision floating-point—Four 32-bit floating-point or two 64-bit floating-point values packed into a 128-bit double quadwordx86 Numeric Data FormatsARM Data Types•8 (byte), 16 (halfword), 32 (word) bits•Halfword and word accesses should be word aligned•Nonaligned access alternatives—Default–Treated as truncated–Bits[1:0] treated as zero for word –Bit[0] treated as zero for halfword–Load single word instructions rotate right word aligned data transferred by non word-aligned address one, two or three bytesAlignment checking—Data abort signal indicates alignment fault for attempting unaligned access—Unaligned access—Processor uses one or more memory accesses to generate transfer of adjacent bytes transparently to the programmer•Unsigned integer interpretation supported for all types•Twos-complement signed integer interpretation supported for all types•Majority of implementations do not provide floating-point hardware—Saves power and area—Floating-point arithmetic implemented in software—Optional floating-point coprocessor—Single- and double-precision IEEE 754 floating point data typesARM Endian Support•E-bit in system control register•Under program controlTypes of Operation•Data Transfer•Arithmetic•Logical•Conversion•I/O•System Control•Transfer of ControlData Transfer•Specify—Source—Destination—Amount of data•May be different instructions for different movements—e.g. IBM 370•Or one instruction and different addresses—e.g. VAXArithmetic•Add, Subtract, Multiply, Divide•Signed Integer•Floating point ?•May include—Increment (a++)—Decrement (a--)—Negate (-a)Shift and Rotate OperationsLogical•Bitwise operations•AND, OR, NOTConversion•E.g. Binary to DecimalInput/Output•May be specific instructions•May be done using data movement instructions (memory mapped)•May be done by a separate controller (DMA)Systems Control•Privileged instructions•CPU needs to be in specific state —Ring 0 on 80386+—Kernel mode•For operating systems useTransfer of Control•Branch—e.g. branch to x if result is