Table 16.1 Machine Instruction Set for Wilkes Example Order Effect of Order A n C(Acc) + C(n) to Acc1 S n C(Acc) – C(n) to Acc1 H n C(n) to Acc2 V n C(Acc2) × C(n) to Acc, where C(n) ≥ 0 T n C(Acc1) to n, 0 to Acc U n C(Acc1) to n R n C(Acc) × 2–(n+1) to Acc L n C(Acc) × 2n+1 to Acc G n IF C(Acc) < 0, transfer control to n; if C(Acc) ≥ 0, ignore (i.e., proceed serially) I n Read next character on input mechanism into n O n Send C(n) to output mechanism Notation: Acc = accumulator Acc1 = most significant half of accumulator Acc2 = least significant half of accumulator n = storage location n C(X) = contents of X (X = register or storage location)Table 16.2 Microinstructions for Wilkes Example (page 1 of 2) Notation: A, B, C,... stand for the various registers in the arithmetical and control register units. C to D indicates that the switching circuits connect the output of register C to the input register D; (D + A) to C indicates that the output register of A is connected to the one input of the adding unit (the output of D is permanently connected to the other input), and the output of the adder to register C. A numerical symbol n in quotes (e.g., 'n') stands for the source whose output is the number n in units of the least significant digit. Arithmetical Unit Control Register Unit Conditional Flip-Flop Next Micro-instruction Set Use 0 1 0 F to G and E 1 1 (G to '1') to F 2 2 Store to G 3 3 G to E 4 4 E to decoder — A 5 C to D 16 S 6 C to D 17 H 7 Store to B 0 V 8 Store to A 27 T 9 C to Store 25 U 10 C to Store 0 R 11 B to D E to G 19 L 12 C to D E to G 22 G 13 E to G (1)C5 18 I 14 Input to Store 0 O 15 Store to Output 0 16 (D + Store) to C 0 17 (D – Store) to C 0 18 1 0 1 19 D to B (R)* (G – '1') to E 20 20 C to D (1)E5 21Table 16.2 Microinstructions for Wilkes Example (page 2 of 2) 21 D to C (R) 1 11 0 22 D to C (L)† (G – ‘1’) to E 23 23 B to D (1)E5 24 24 D to B (L) 1 12 0 25 ‘0’ to B 26 26 B to C 0 27 ‘0’ to C ‘18’ to E 28 28 B to D E to G (1)B1 29 29 D to B (R) (G – ‘1’) to E 30 30 C to D (R) (2)E5 1 31 32 31 D to C 2 28 33 32 (D + A) to C 2 28 33 33 B to D (1)B1 34 34 D to B (R) 35 35 C to D (R) 1 36 37 36 D to C 0 37 (D – A) to C 0 *Right shift. The switching circuits in the arithmetic unit are arranged so that the least significant digit of the register C is placed in the most significant place of register B during right shift micro-operations, and the most significant digit of register C (sign digit) is repeated (thus making the correction for negative numbers). †Left shift. The switching circuits are similarly arranged to pass the most significant digit of register B to the least significant place of register C during left shift micro-operations.Table 16.3 Microinstruction Address Generation Techniques Explicit Implicit Two-field Mapping Unconditional branch Addition Conditional branch Residual controlTable 16.4 The Microinstruction Spectrum Characteristics Unencoded Highly encoded Many bits Few bits Detailed view of hardware Aggregated view of hardware Difficult to program Easy to program Concurrency fully exploited Concurrency not fully exploited Little or no control logic Complex control logic Fast execution Slow execution Optimize performance Optimize programming Terminology Unpacked Packed Horizontal Vertical Hard SoftTable 16.5 Some LSI-11 Microinstructions Arithmetic Operations Add word (byte, literal) Test word (byte, literal) Increment word (byte) by 1 Increment word (byte) by 2 Negate word (byte) Conditionally increment (decrement) byte Conditionally add word (byte) Add word (byte) with carry Conditionally add digits Subtract word (byte) Compare word (byte, literal) Subtract word (byte) with carry Decrement word (byte) by 1 Logical Operations AND word (byte, literal) Test word (byte) OR word (byte) Exclusive-OR word (byte) Bit clear word (byte) Shift word (byte) right (left) with (without) carry Complement word (byte) General Operations MOV word (byte) Jump Return Conditional jump Set (reset) flags Load G low Conditionally MOV word (byte) Input/Output Operations Input word (byte) Input status word (byte) Read Write Read (write) and increment word (byte) by 1 Read (write) and increment word (byte) by 2 Read (write) acknowledge Output word (byte, status)Table 16.6 IBM 3033 Microinstruction Control Fields ALU Control Fields AA(3) Load A register from one of data registers AB(3) Load B register from one of data registers AC(3) Load C register from one of data registers AD(3) Load D register from one of data registers AE(4) Route specified A bits to ALU AF(4) Route specified B bits to ALU AG(5) Specifies ALU arithmetic operation on A input AH(4) Specifies ALU arithmetic operation on B input AJ(1) Specifies D or B input to ALU on B side AK(4) Route arithmetic output to shifter CA(3) Load F register CB(1) Activate shifter CC(5) Specifies logical and carry functions CE(7) Specifies shift amount Sequencing and Branching Fields AL(1) End operation and perform branch BA(8) Set high-order bits (00–07) of control address register BB(4) Specifies condition for setting bit 8 of control address register BC(4) Specifies condition for setting bit 9 of control address register BD(4) Specifies condition for setting bit 10 of control address register BE(4) Specifies condition for setting bit 11 of control address register BF(7) Specifies condition for setting bit 12 of control address registerTable 16.7 TI 8800 Microinstruction Format Field Number Number of Bits Description Control of Board 1 5 Select condition code input 2 1 Enable/disable external I/O request signal 3 2 Enable/disable local data memory read/write operations 4 1 Load status/do no load status 5 2 Determine unit driving Y bus 6 2 Determine unit driving DA bus 8847 Floating Point and Integer Processing Chip 7 1 C register control: clock, do not clock 8 1 Select most significant or least significant bits for Y bus 9 1 C register data source: ALU, multiplexer 10 4 Select IEEE or FAST mode for ALU and MUL 11 8 Select sources for data operands: RA registers, RB registers, P register, 5 register, C register 12 1 RB register control: clock, do not clock 13 1 RA register control: clock, do not clock 14 2 Data source confirmation 15 2 Enable/disable pipeline