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CSUN COMP 546 - Vertical

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Table 2.1 The IAS Instruction Set Instruction Type Opcode Symbolic Representation Description 00001010 LOAD MQ Transfer contents of register MQ to the accumulator AC 00001001 LOAD MQ,M(X) Transfer contents of memory location X to MQ 00100001 STOR M(X) Transfer contents of accumulator to memory location X 00000001 LOAD M(X) Transfer M(X) to the accumulator 00000010 LOAD –M(X) Transfer –M(X) to the accumulator 00000011 LOAD |M(X)| Transfer absolute value of M(X) to the accumulator Data transfer 00000100 LOAD –|M(X)| Transfer –|M(X)| to the accumulator 00001101 JUMP M(X,0:19) Take next instruction from left half of M(X) Unconditional branch 00001110 JUMP M(X,20:39) Take next instruction from right half of M(X) 00001111 JUMP+ M(X,0:19) If number in the accumulator is nonnegative, take next instruction from left half of M(X) Conditional branch 00010000 JUMP+ M(X,20:39) If number in the accumulator is nonnegative, take next instruction from right half of M(X) 00000101 ADD M(X) Add M(X) to AC; put the result in AC 00000111 ADD |M(X)| Add |M(X)| to AC; put the result in AC 00000110 SUB M(X) Subtract M(X) from AC; put the result in AC 00001000 SUB |M(X)| Subtract |M(X)| from AC; put the remainder in AC 00001011 MUL M(X) Multiply M(X) by MQ; put most significant bits of result in AC, put least significant bits in MQ 00001100 DIV M(X) Divide AC by M(X); put the quotient in MQ and the remainder in AC 00010100 LSH Multiply accumulator by 2; i.e., shift left one bit position Arithmetic 00010101 RSH Divide accumulator by 2; i.e., shift right one position 00010010 STOR M(X,8:19) Replace left address field at M(X) by 12 rightmost bits of AC Address modify 00010011 STOR M(X,28:39) Replace right address field at M(X) by 12 rightmost bits of ACTable 2.2 Computer Generations Generation Approximate Dates Technology Typical Speed (operations per second) 1 1946–1957 Vacuum tube 40,000 2 1958–1964 Transistor 200,000 3 1965–1971 Small and medium scale integration 1,000,000 4 1972–1977 Large scale integration 10,000,000 5 1978–1991 Very large scale integration 100,000,000 6 1991- Ultra large scale integration 1,000,000,000Table 2.4 Key Characteristics of the System/360 Family Characteristic Model 30 Model 40 Model 50 Model 65 Model 75 Maximum memory size (bytes) 64K 256K 256K 512K 512K Data rate from memory (Mbytes/sec) 0.5 0.8 2.0 8.0 16.0 Processor cycle time µs) 1.0 0.625 0.5 0.25 0.2 Relative speed 1 3.5 10 21 50 Maximum number of data channels 3 3 4 6 6 Maximum data rate on one channel (Kbytes/s) 250 400 800 1250 1250Table 2.7 Examples of Embedded Systems and Their Markets [NOER05] Market Embedded Device Automotive Ignition system Engine control Brake system Consumer electronics Digital and analog televisions Set-top boxes (DVDs, VCRs, Cable boxes) Personal digital assistants (PDAs) Kitchen appliances (refrigerators, toasters, microwave ovens) Automobiles Toys/games Telephones/cell phones/pagers Cameras Global positioning systems Industrial control Robotics and controls systems for manufacturing Sensors Medical Infusion pumps Dialysis machines Prosthetic devices Cardiac monitors Office automation Fax machine Photocopier Printers Monitors ScannersTable 2.8 ARM Evolution Family Notable Features Cache Typical MIPS @ MHz ARM1 32-bit RISC None ARM2 Multiply and swap instructions; Integrated memory management unit, graphics and I/O processor None 7 MIPS @ 12 MHz ARM3 First use of processor cache 4 KB unified 12 MIPS @ 25 MHz ARM6 First to support 32-bit addresses; floating-point unit 4 KB unified 28 MIPS @ 33 MHz ARM7 Integrated SoC 8 KB unified 60 MIPS @ 60 MHz ARM8 5-stage pipeline; static branch prediction 8 KB unified 84 MIPS @ 72 MHz ARM9 16 KB/16 KB 300 MIPS @ 300 MHz ARM9E Enhanced DSP instructions 16 KB/16 KB 220 MIPS @ 200 MHz ARM10E 6-stage pipeline 32 KB/32 KB ARM11 9-stage pipeline Variable 740 MIPS @ 665 MHz Cortex 13-stage superscalar pipeline Variable 2000 MIPS @ 1 GHz XScale Applications processor; 7-stage pipeline 32 KB/32 KB L1 512 KB L2 1000 MIPS @ 1.25 GHz DSP = digital signal processor SoC = system on a chipTable 2.9 Performance Factors and System Attributes Ic p m k τ Instruction set architecture X X Compiler technology X X X Processor implementation X X Cache and memory hierarchy X


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