1EE 4504 Section 8 1EE 4504Computer OrganizationSection 8The CPU StructureEE 4504 Section 8 2OverviewThis section investigates how a typicalCPU is organized– Major components (revisited)– Register organization– The instruction cycle (revisited)– Instruction pipelining– Pentium and PowerPC case studiesReading: Text, Chapter 11 (Sections 1 --4), Chapter 13 (Sections 1 and 2)2EE 4504 Section 8 3CPU organizationRecall the functions performed by theCPU:– Fetch instructions– Fetch data– Process data– Write dataOrganizational requirements that arederived from these functions:– ALU– Control logic– Temporary storage– Means to move data and instructions in andaround the CPUEE 4504 Section 8 4Figure 11.1 External view of the CPU3EE 4504 Section 8 5Figure 11.2 Internal structure of the CPUEE 4504 Section 8 6Register OrganizationRegisters form the highest level of thememory hierarchy– Small set of high speed storage locations– Temporary storage for data and controlinformationTwo types of registers– User-visible» May be referenced by assembly-levelinstructions and are thus “visible” to theuser– Control and status registers» Used to control the operation of the CPU» Most are not visible to the user4EE 4504 Section 8 7User-visible RegistersGeneral categories based on function– General purpose» Can be assigned a variety of functions» Ideally, they are defined orthogonally to theoperations within the instructions– Data» These registers only hold data– Address» These registers only hold addressinformation» Examples: general purpose addressregisters, segment pointers, stack pointers,index registers– Condition codes» Visible to the user but values set by theCPU as the result of performing operations» Example code bits: zero, positive, overflow» Bit values are used as the basis forconditional jump instructionsEE 4504 Section 8 8Design trade off between general purposeand specialized registers– General purpose registers maximize flexibilityin instruction design– Special purpose registers permit implicitregister specification in instructions -- reducesregister field size in an instruction– No clear “best” design approachHow many registers are enough– More registers permit more operands to be heldwithin the CPU -- reducing memory bandwidthrequirements to some extent– More registers cause an increase in the fieldsizes needed to specify registers in aninstruction word– Locality of reference may not support too manyregisters– Most machines use 8-32 registers (does notinclude RISC machines with registerwindowing -- will get to that later!)5EE 4504 Section 8 9How big (wide)– Address registers should be wide enough tohold the longest address address!– Data registers should be wide enough to holdmost data types» Would not want to use 64-bit registers if thevast majority of data operations used 16 and32-bit operands» Related to width of memory data bus» Concatenate registers together to storelonger formatsB-C registers in the 8085AccA-AccB registers in the 68HC11EE 4504 Section 8 10Control and status registersThese registers are used during thefetching, decoding and execution ofinstructions– Many are not visible to the user/programmer– Some are visible but can not be (easily)modifiedTypical registers– Program counter» Points to the next instruction to be executed– Instruction register» Contains the instruction being executed– Memory address register– Memory data/buffer register– Program status word(s)» Superset of condition code register» Interrupt masks, supervisory modes, etc.» Status information6EE 4504 Section 8 11Figure 11.3 Example register organizationsEE 4504 Section 8 12Figure 11.4 Extensions to 32 bits microprocessors7EE 4504 Section 8 13Instruction CycleRecall the instruction cycle from Chapter3:– Fetch the instruction– Decode it– Fetch operands– Perform the operation– Store results– Recognize pending interruptsBased on the addressing techniques fromChapter 9, we can modify the statediagram for the cycle to explicitly showindirection in addressingFlow of data and information betweenregisters during the instruction cycle variesfrom processor to processorEE 4504 Section 8 14Figure 11.7 More complete instruction cycle state diagram8EE 4504 Section 8 15Instruction pipeliningThe instruction cycle state diagram clearlyshows the sequence of operations that takeplace in order to execute a singleinstructionA “good” design goal of any system is tohave all of its components performinguseful work all of the time -- highefficiencyFollowing the instruction cycle in asequential fashion does not permit thislevel of efficiencyCompare the instruction cycle to anautomobile assembly line– Perform all tasks concurrently, but on different(sequential) instructions– The result is temporal parallelism– Result is the instruction pipelineEE 4504 Section 8 16An ideal pipeline divides a task into kindependent sequential subtasks– Each subtask requires 1 time unit to complete– The task itself then requires k time units tocompleteFor n iterations of the task, the executiontimes will be:– With no pipelining: nk time units– With pipelining: k + (n-1) time unitsSpeedup of a k-stage pipeline is thusS = nk / [k+(n-1)] ==> k (for large n)9EE 4504 Section 8 17First step: instruction (pre)fetch– Divide the instruction cycle into two (equal??)“parts”» I-fetch» Everything else (execution phase)– While one instruction is in “execution,” overlapthe prefetching of the next instruction» Assumes the memory bus will be idle atsome point during the execution phase» Reduces the time to fetch an instruction tozero (ideal situation)– Problems» The two parts are not equal in size» Branching can negate the prefetchingAs a result of the brach instruction, youhave prefetched the “wrong”instructionEE 4504 Section 8 18– Alternative approaches» Finer division of the instruction cycle: usea 6-stage pipelineInstruction fetchDecode opcodeCalculate operand address(es)Fetch operandsPerform executionWrite (store) result» Use multiple execution “functional units” toparallelize the actual execution phase ofseveral instructions» Use branching strategies to minimizebranch impact10EE 4504 Section 8 19Figure 11.12 Pipelined execution of 9 instructionsin 14 time units vs. 54EE 4504 Section 8 20Figure 11.13 Impact of a branch after instruction 3 (to instruction 15)11EE 4504 Section 8 21Pipeline