William Stallings Computer Organization and Architecture 8th EditionInput/Output ProblemsInput/Output ModuleGeneric Model of I/O ModuleExternal DevicesExternal Device Block DiagramI/O Module FunctionI/O StepsI/O Module DiagramI/O Module DecisionsInput Output TechniquesThree Techniques for Input of a Block of DataProgrammed I/OProgrammed I/O - detailI/O CommandsAddressing I/O DevicesI/O MappingMemory Mapped and Isolated I/OInterrupt Driven I/OInterrupt Driven I/O Basic OperationSimple Interrupt ProcessingCPU ViewpointChanges in Memory and Registers for an InterruptDesign IssuesIdentifying Interrupting Module (1)Identifying Interrupting Module (2)Multiple InterruptsExample - PC BusSequence of EventsISA Bus Interrupt System82C59A Interrupt ControllerIntel 82C55A Programmable Peripheral InterfaceKeyboard/Display Interfaces to 82C55ADirect Memory AccessDMA FunctionTypical DMA Module DiagramDMA OperationDMA Transfer Cycle StealingDMA and Interrupt Breakpoints During an Instruction CycleAsideDMA Configurations (1)DMA Configurations (2)DMA Configurations (3)Intel 8237A DMA Controller8237 DMA Usage of Systems BusFly-ByI/O ChannelsI/O Channel ArchitectureInterfacingIEEE 1394 FireWireFireWire ConfigurationSimple FireWire ConfigurationFireWire 3 Layer StackFireWire Protocol StackFireWire - Physical LayerFireWire - Link LayerFireWire SubactionsInfiniBandInfiniBand ArchitectureInfiniBand Switch FabricInfiniBand OperationInfiniBand Protocol StackForeground ReadingWilliam Stallings Computer Organization and Architecture8th EditionChapter 7Input/OutputInput/Output Problems•Wide variety of peripherals—Delivering different amounts of data—At different speeds—In different formats•All slower than CPU and RAM•Need I/O modulesInput/Output Module•Interface to CPU and Memory•Interface to one or more peripheralsGeneric Model of I/O ModuleExternal Devices•Human readable—Screen, printer, keyboard•Machine readable—Monitoring and control•Communication—Modem—Network Interface Card (NIC)External Device Block DiagramI/O Module Function•Control & Timing•CPU Communication•Device Communication•Data Buffering•Error DetectionI/O Steps•CPU checks I/O module device status•I/O module returns status•If ready, CPU requests data transfer•I/O module gets data from device•I/O module transfers data to CPU•Variations for output, DMA, etc.I/O Module DiagramI/O Module Decisions•Hide or reveal device properties to CPU•Support multiple or single device•Control device functions or leave for CPU•Also O/S decisions—e.g. Unix treats everything it can as a fileInput Output Techniques•Programmed•Interrupt driven•Direct Memory Access (DMA)Three Techniques for Input of a Block of DataProgrammed I/O•CPU has direct control over I/O—Sensing status—Read/write commands—Transferring data•CPU waits for I/O module to complete operation•Wastes CPU timeProgrammed I/O - detail•CPU requests I/O operation•I/O module performs operation•I/O module sets status bits•CPU checks status bits periodically•I/O module does not inform CPU directly•I/O module does not interrupt CPU•CPU may wait or come back laterI/O Commands•CPU issues address—Identifies module (& device if >1 per module)•CPU issues command—Control - telling module what to do–e.g. spin up disk—Test - check status–e.g. power? Error?—Read/Write–Module transfers data via buffer from/to deviceAddressing I/O Devices•Under programmed I/O data transfer is very like memory access (CPU viewpoint)•Each device given unique identifier•CPU commands contain identifier (address)I/O Mapping•Memory mapped I/O—Devices and memory share an address space—I/O looks just like memory read/write—No special commands for I/O–Large selection of memory access commands available•Isolated I/O—Separate address spaces—Need I/O or memory select lines—Special commands for I/O–Limited setMemory Mapped and Isolated I/OInterrupt Driven I/O•Overcomes CPU waiting•No repeated CPU checking of device•I/O module interrupts when readyInterrupt Driven I/OBasic Operation•CPU issues read command•I/O module gets data from peripheral whilst CPU does other work•I/O module interrupts CPU•CPU requests data•I/O module transfers dataSimple InterruptProcessingCPU Viewpoint•Issue read command•Do other work•Check for interrupt at end of each instruction cycle•If interrupted:-—Save context (registers)—Process interrupt–Fetch data & store•See Operating Systems notesChanges in Memory and Registersfor an InterruptDesign Issues•How do you identify the module issuing the interrupt?•How do you deal with multiple interrupts?—i.e. an interrupt handler being interruptedIdentifying Interrupting Module (1)•Different line for each module—PC—Limits number of devices•Software poll—CPU asks each module in turn—SlowIdentifying Interrupting Module (2)•Daisy Chain or Hardware poll—Interrupt Acknowledge sent down a chain—Module responsible places vector on bus—CPU uses vector to identify handler routine•Bus Master—Module must claim the bus before it can raise interrupt—e.g. PCI & SCSIMultiple Interrupts•Each interrupt line has a priority•Higher priority lines can interrupt lower priority lines•If bus mastering only current master can interruptExample - PC Bus•80x86 has one interrupt line•8086 based systems use one 8259A interrupt controller•8259A has 8 interrupt linesSequence of Events•8259A accepts interrupts•8259A determines priority•8259A signals 8086 (raises INTR line)•CPU Acknowledges•8259A puts correct vector on data bus•CPU processes interruptISA Bus Interrupt System•ISA bus chains two 8259As together•Link is via interrupt 2•Gives 15 lines—16 lines less one for link•IRQ 9 is used to re-route anything trying to use IRQ 2—Backwards compatibility•Incorporated in chip set82C59A InterruptControllerIntel 82C55A Programmable Peripheral InterfaceKeyboard/Display Interfaces to 82C55ADirect Memory Access•Interrupt driven and programmed I/O require active CPU intervention—Transfer rate is limited—CPU is tied up•DMA is the answerDMA Function•Additional Module (hardware) on bus•DMA controller takes over from CPU for I/OTypical DMA Module DiagramDMA Operation•CPU tells DMA controller:-—Read/Write—Device address—Starting address of memory block for data—Amount of data to be transferred•CPU carries on with other