EEC 118 Lecture #8: CMOS Logic Transient CharacteristicsAnnouncementsOutlineReview: Static CMOSReview: Dual NetworksReview: Equivalent InverterGraph-Based Dual NetworkPropagation Delay Analysis - The Switch ModelSwitch Level ModelWhat is the Value of Ron? Switch Level Model DelaysSwitch Level Model RC DelaysNumerical ExamplesAnalysis of Propagation DelayDesign for Worst CaseFan-In and Fan-Out Fast Complex Gates - Design TechniquesFast Complex Gates - Design Techniques (2)Fast Complex Gates - Design Techniques (3)Fast Complex Gates - Design Techniques (4)4 Input NAND GateCapacitances in a 4 input NAND GateNext Topic: Sequential Logic AnnouncementsAnnouncementsMidtermFormulas for MidtermEEC 118 Lecture #8:CMOS Logic Transient CharacteristicsRajeevan AmirtharajahUniversity of California, DavisJeff ParkhurstIntel CorporationAmirtharajah/Parkhurst, EEC 118 Spring 2010 2Announcements• Quiz 2 on Monday, April 26• Midterm on Monday, May 3– Covers material through Lecture (Monday 4/26)• HW4 due Friday, 4PM in box, Kemper 2131• Lab 3, Part 2 report due next weekAmirtharajah/Parkhurst, EEC 118 Spring 2010 3Outline• Review: Static CMOS Logic• Finish equivalent inverter discussion• Combinational MOS Logic Circuits: Rabaey 6.1-6.2, 7.1-7.3 (Kang & Leblebici, 7.1-7.4)Amirtharajah/Parkhurst, EEC 118 Spring 2010 4Review: Static CMOS• Complementary pullupnetwork (PUN) and pulldownnetwork (PDN)• Only one network is on at a time• PUN: PMOS devices–Why? VOH= VDD• PDN: NMOS devices–Why? VOL= 0 V• PUN and PDN are dual networksPUNPDNFABCABCAmirtharajah/Parkhurst, EEC 118 Spring 2010 5Review: Dual NetworksBAF• Dual networks: parallel connection in PDN = series connection in PUN, vice-versa• If CMOS gate implements logic function F:– PUN implements function F– PDN implements function G = FExample: NAND gateparallelseriesAmirtharajah/Parkhurst, EEC 118 Spring 2010 6Review: Equivalent Inverter• Represent complex gate as inverter for delay estimation, VTC analysis• Use worse-case conditions for delays• Example: NAND gate– Worse-case (slowest) pull-up: only 1 PMOS “on”– Pull-down: both NMOS “on”WNWNWPWPWP½WNAmirtharajah/Parkhurst, EEC 118 Spring 2010 7BGraph-Based Dual Network• Use graph theory to help design gates– Mostly implemented in CAD tools• Draw network for PUN or PDN– Circuit nodes are vertices– Transistors are edgesAFgndABFAmirtharajah/Parkhurst, EEC 118 Spring 2010 8Graph-Based Dual Network (2)• To derive dual network:– Create new node in each enclosed region of graph– Draw new edge intersecting each original edge– Edge is controlled by inverted inputABABABFAmirtharajah/Parkhurst, EEC 118 Spring 2010 9Propagation Delay Analysis - The Switch ModelVDDVDDVDDCLFCLCLFFRpRpRpRpRpRnRnRnRnRnAAAAAABBBB(a) Inverter(b) 2-input NAND(c) 2-input NORtp= 0.69 RonCL(assuming that CL dominates!)= RONAmirtharajah/Parkhurst, EEC 118 Spring 2010 10Switch Level Model• Model transistors as switches with series resistance• Resistance Ron= average resistance for a transition• Capacitance CL= average load capacitance for a transition (same as we analyzed for transient inverter delays)RNRPAACLAmirtharajah/Parkhurst, EEC 118 Spring 2010 11What is the Value of Ron?Amirtharajah/Parkhurst, EEC 118 Spring 2010 12Switch Level Model DelaysDelay estimation using switch-level model (for general RC circuit):RNCL[]⎟⎟⎠⎞⎜⎜⎝⎛=−===−=→==→=∫010101ln)ln()ln( 10VVRCVVRCtdVVRCtttdVVRCdtRVIdVICdtdtdVCIpVVpAmirtharajah/Parkhurst, EEC 118 Spring 2010 13Switch Level Model RC Delays• For fall delay tphl, V0=VDD, V1=VDD/2LpplhLnphlpDDDDpCRtCRtRCtVVRCVVRCt69.069.0)5.0ln(lnln2101===⎟⎟⎠⎞⎜⎜⎝⎛=⎟⎟⎠⎞⎜⎜⎝⎛=Standard RC-delay equations from literatureAmirtharajah/Parkhurst, EEC 118 Spring 2010 14Numerical Examples• Example resistances for 1.2 μm CMOSAmirtharajah/Parkhurst, EEC 118 Spring 2010 15Analysis of Propagation DelayVDDCLFRpRpRnRnAABB2-input NAND1. Assume Rn=Rp= resistance of minimum sized NMOS inverter2. Determine “Worst Case Input” transition(Delay depends on input values)3. Example: tpLH for 2input NAND- Worst case when only ONE PMOS Pullsup the output node- For 2 PMOS devices in parallel, the resistance is lower4. Example: tpHL for 2input NAND- Worst case : TWO NMOS in seriestpLH = 0.69RpCLtpHL = 0.69(2Rn)CLAmirtharajah/Parkhurst, EEC 118 Spring 2010 16Design for Worst CaseVDDCLFAABB2211VDDABCDDABC12222244FHere it is assumed that Rp = Rn NAND Gate Complex GateAmirtharajah/Parkhurst, EEC 118 Spring 2010 17Fan-In and Fan-Out VDDABABCDCDFan-OutNumber of logic gates connected to output(2 FET gate capacitances per fan-out)Fan-In Number of logical inputsQuadratic delay term due to:1.Resistance increasing2.Capacitance increasingfor tpHL(series NMOS)tpproportional to a1FI + a2FI2+ a3FOAmirtharajah/Parkhurst, EEC 118 Spring 2010 18Fast Complex Gates - Design Techniques• Increase Transistor Sizing: Works as long as Fan-out capacitance dominates self capacitance (S/D cap increases with increased width)• Progressive Sizing:CLIn1InNIn3In2OutC1C2C3M 1 > M 2 > M 3 > MNM1M2M3MNDistributed RC-lineCan Reduce Delay by more than 30%!Amirtharajah/Parkhurst, EEC 118 Spring 2010 19In1In3In2C1C2CLM1M2M3In3In1In2C3C2CLM3M2M1(a) (b)• Transistor Orderingcritical pathcritical pathPlace last arriving input closest to output nodeFast Complex Gates - Design Techniques (2)Amirtharajah/Parkhurst, EEC 118 Spring 2010 20Fast Complex Gates - Design Techniques (3)• Improved Logic DesignNote Fan-Out capacitance is the same, but Fan-In resistance lower for input gates (fewer series FETs)Amirtharajah/Parkhurst, EEC 118 Spring 2010 21Fast Complex Gates - Design Techniques (4)• Buffering: Isolate Fan-in from Fan-outCLCLKeeps high fan-in resistance isolated from large capacitive load CLAmirtharajah/Parkhurst, EEC 118 Spring 2010 224 Input NAND GateIn3In1In2In4In1In2In3In4VDDOutIn1In2In3 In4VDDGNDOutAmirtharajah/Parkhurst, EEC 118 Spring 2010 23Capacitances in a 4 input NAND GateNote that the value of Cload for calculating propagation delay depends on which capacitances need to be discharged or charged when the critical signal arrives.Example: In1= In3= In4= 1. In2 = 0. In2switches from low to high. Hence, Nodes 3 and 4 are already discharged to ground. In order for Vout to go from high to low… Voutnode and node 2 must be discharged.CL = Cgd5+Cgd7+Cgd8+2Cgd6(Miller)+Cdb5+Cdb6+Cdb7+Cdb8 +Cgd1+ Cdb1+ Cgs1+ Csb1+ 2Cgd2+ Cdb2+