EEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic FamiliesAnnouncementsAnnouncementsOutlineReview: CMOS SizingReview of SizingExample: NAND gateEquivalent InverterLoad CapacitanceIntermediate Node CapacitancesCMOS Design Guidelines ICMOS Design Guidelines IICMOS DisadvantagesPseudo-NMOS LogicPseudo-NMOS Inverter CircuitPseudo-NMOS Inverter: VOHPseudo-NMOS Inverter: VOLPseudo NMOS Inverter: I/V CurvesTransmission Gate LogicEquivalent Transmission Gate ResistanceEquivalent ResistanceResistance ApproximationsEquivalent Resistance – Region 1Equivalent Resistance – Region 2Equivalent Resistance – Region 3Transmission Gate LogicTransmission Gate XORTransmission Gate MultiplexerFull Transmission Gate LogicNext Topic: Dynamic Circuits AnnouncementsEEC 118 Lecture #11:CMOS Design GuidelinesAlternative Static Logic FamiliesRajeevan AmirtharajahUniversity of California, DavisJeff ParkhurstIntel CorporationAmirtharajah/Parkhurst, EEC 118 Spring 2010 4Outline• Finish Arithmetic Discussion• Review: Static CMOS Sizing• Design Guidelines for CMOS• Pseudo-NMOS Logic: Rabaey 6.2• Pass Transistor Circuits: Rabaey 6.2 (Kang & Leblebici 9.1-9.2)Amirtharajah/Parkhurst, EEC 118 Spring 2010 5Review: CMOS Sizing• Equivalent inverter approach: replace transistors which are “on” with equivalent transistor• Use equivalent inverter to find VM, delays, etc.if A=0, B switches:ABABFWnaWnbWpbWpaWpeffWneffBFnbneffpbpapeffWWWWW=+=111Amirtharajah/Parkhurst, EEC 118 Spring 2010 6Review of Sizing• Gate delays depend on which inputs switch– Normally sized for worst-case delay– Best-case (fastest) delay also important due to race conditions in a pipelined datapath• Switching threshold VMnormally considers all inputs switching• Delay estimation– Combine switching transistors into equivalent inverterAmirtharajah/Parkhurst, EEC 118 Spring 2010 7Example: NAND gate• Circuit: – Load cap CL=400fF–PMOS W/L = 2–NMOS W/L = 1–kn’ = 200 mA/V2–kp’ = 80 mA/V2–VT= 0.5V• 1st: Find delay of inverter• 2nd: Find delay of NANDAFWnWpBCAWpBWpCWnWnAmirtharajah/Parkhurst, EEC 118 Spring 2010 8Equivalent Inverter• Problems with equivalent inverter method:– Need to take into account load capacitance CL• Depends on number of transistors connected to output (junction capacitances)• Even transistors which are off (not included in equivalent inverter) contribute to capacitance (i.e. PMOS Drain Capacitance)– Need to include capacitance in intermediate stack nodes (NMOS caps). Worst-case: need to charge/discharge all nodes– Body effect of stacked transistorsAmirtharajah/Parkhurst, EEC 118 Spring 2010 9Load Capacitance• Output capacitance includes junction caps of all transistors on output• Reducing load capacitance– Minimize number of transistors on output node– Tapering transistor stacks:• Wider transistors closest to power and ground nodes, narrower at output• Transistors closest to power nodes carry more currentAmirtharajah/Parkhurst, EEC 118 Spring 2010 10Intermediate Node Capacitances• Internal capacitances in CMOS gates are charged and discharged– Depends on input pattern– Increases delay of gate• Simple analysis– Combine internal capacitances into output load– Assumes all capacitances charged and discharged fully• Effect on delay analysis– Gate delay depends on timing of inputs!Amirtharajah/Parkhurst, EEC 118 Spring 2010 11CMOS Design Guidelines I• Transistor sizing– Size for worst-case delay, threshold, etc– Tapering: transistors near power supply are larger than transistors near output• Transistor ordering– Critical signal is defined as the latest-arriving signal to input of gate of interest.– Put critical signals closest to output• Stack nodes are discharged by early signals• Reduced body effect on top transistorAmirtharajah/Parkhurst, EEC 118 Spring 2010 12CMOS Design Guidelines II• Limit fan-in of gate– Fan-in: number of gate inputs– Affects size of transistor stacks– Normally fan-in limit is 3-4• Convert large multi-input gates into smaller chain of gates• Limit fanout of gate– Fanout: number of gates connected to output– Capacitive load: affects gate delay• NANDs are better than NORs– Series NMOS devices less area, capacitance than equivalent series PMOS devicesAmirtharajah/Parkhurst, EEC 118 Spring 2010 13CMOS Disadvantages• For N-input CMOS gate, 2N transistors required– Each input connects to an NMOS and PMOS transistor– Large input capacitance: limits fanout• Large fan-in gates: always have long transistor stack in PUN or PDN– Limits pullup or pulldown delay– Requires very large transistors• Single-stage gates are invertingAmirtharajah/Parkhurst, EEC 118 Spring 2010 14Pseudo-NMOS Logic• Pseudo-NMOS: replace PMOS PUN with single “always-on” PMOS device (grounded gate)• Same problems as true NMOS inverter:–VOLlarger than 0 V– Static power dissipation when PDN is on• Advantages– Replace large PMOS stacks with single device– Reduces overall gate size, input capacitance– Especially useful for wide-NOR structuresAmirtharajah/Parkhurst, EEC 118 Spring 2010 15Pseudo-NMOS Inverter Circuit• Replace PUN or resistor with “always-on” PMOS transistor• Easier to implement in standard process than large resistance value• PMOS load transistor:– On when VGS< VTP→VGS= -VDD: transistor always on– Linear when VDS> VGS-VTP→Vout-VDD> -VDD-VTP→ Vout> -VTP– Saturated when VDS< VGS-VT→Vout-VDD< -VDD-VTP→ Vout< -VTPVinVDDGndGSDVGS,P= -VDDVoutRemember: VT (PMOS) < 0Amirtharajah/Parkhurst, EEC 118 Spring 2010 16Pseudo-NMOS Inverter: VOH• VOHfor pseudo-NMOS inverter:–Vin = 0– NMOS in cutoff: no drain current• Result: VOHis VDD(as in resistive-load inverter or CMOS inverter case)VDDGndVoutAmirtharajah/Parkhurst, EEC 118 Spring 2010 17Pseudo-NMOS Inverter: VOL• Find VOL of pseudo-NMOS inverter: –Vin= VDD: NMOS on in linear mode (assume VOL< VDD-VT,n)()[]221OLOLTnDDnDnVVVVkI −−=– PMOS on in saturation mode (assume)()221TpDDpDpVVkI −−=(neglecting λ)– Setting Idn= Idp:()()0221221=−−+−−TpDDpOLTnDDnOLnVVkVVVkVk• Key point: VOLis not zero – Depends on thresholds, sizes of N and P transistorsAmirtharajah/Parkhurst, EEC 118 Spring 2010 18Pseudo NMOS Inverter: I/V CurvesVDS= VoutDrain current IDSVin=2VVDDVin=1VVin=3VVin=4V-VDS= -(Vout-VDD)-Drain current -IDSI/V curve for NMOS: I/V curve for PMOS:VGS=-VDD• Plot of -IDSvs