EEC 118 Lecture #1: MOSFET OverviewPermissions to Use Conditions & AcknowledgmentOutlinePersonnelCourse MaterialsGradingWeightingLabs and CAD Software UsageEducation Demand for Circuit DesignEducation Demand for System DesignHistorical BackgroundMemory, Processors and GraphicsMemory, Processors and GraphicsHybrid to Monolithic TrendWhat are the issues facing the industry ?Why worry about power? Power DissipationWhy worry about power? Chip Power DensityChip Power Density DistributionRecent Battery Scaling and Future TrendsWhy worry about power? Standby Power Chip Design StylesLogic Design FamiliesDesign ParametersCurrent State of the ArtMoore’s LawExpectationsMOS Transistor TypesMOS Transistor SymbolsNote on MOS Transistor SymbolsMOS Transistor StructureNMOS Transistor I-V Characteristics INMOS Transistor I-V Characteristics IIMOS Transistor Operation: CutoffMOS Transistor Operation: InversionThreshold Voltage ComponentsThreshold Voltage SummaryThreshold Voltage (NMOS vs. PMOS)Body EffectMOS Transistor Regions of OperationMOSFET Drain Current OverviewA Fourth Region: SubthresholdNext Topic: MOSFET DetailsEEC 118 Lecture #1:MOSFET OverviewRajeevan AmirtharajahUniversity of California, DavisJeff ParkhurstIntel CorporationAmirtharajah/Parkhurst, EEC 118 Spring 2010 2Permissions to Use Conditions & Acknowledgment• Permission is granted to copy and distribute this slide set for educational purposes only, provided that the complete bibliographic citation and following credit line is included: "Copyright 2002 J. Rabaey et al." Permission is granted to alter and distribute this material provided that the following credit line is included: "Adapted from (complete bibliographic citation). Copyright 2002 J. Rabaey et al."This material may not be copied or distributed for commercial purposes without express written permission of the copyright holders. • Slides 13-17 Adapted from CSE477 VLSI Digital Circuits Lecture Slides by Vijay Narayanan and Mary Jane Irwin, Penn State UniversityAmirtharajah/Parkhurst, EEC 118 Spring 2010 3Outline• Administrative Details• Survey of Digital IC Technology• MOSFET OverviewAmirtharajah/Parkhurst, EEC 118 Spring 2010 4Personnel• Prof. Raj Amirtharajah (Instructor)Office: 3173 Kemper HallEmail: [email protected] put EEC 118 in email subject line.Office Hours: Th 2 - 3 PM or by appointment.• Mackenzie ScottEmail: [email protected] Hours: (TBD)• Yixuan ZhaiEmail: [email protected] Hours: (TBD)• LabsTuesdays 5 PM – 8 PM 2157/2161 KemperWednesdays 5 PM – 8 PM 2157/2161 KemperAmirtharajah/Parkhurst, EEC 118 Spring 2010 5Course Materials• TextbookDigital Integrated Circuits (2nded.) by J. Rabaey, A. Chandrakasan, and B. Nikolic• Suggested ReferencesCMOS Digital Integrated Circuits (3rded.) Kang and LeblebiciCMOS VLSI Design (3rded.) Weste, Harris• HandoutsLabs, lab report cover sheets, slides, and lecture notes available on course web page in PDF format.• Web Pagehttp://www.ece.ucdavis.edu/~ramirtha/EEC118/S10/S10.htmlLinked from MyUCDavis EEC 118 page and SmartSiteAmirtharajah/Parkhurst, EEC 118 Spring 2010 6Grading• Letter• A: 100 - 90%• B: 90 - 80%• C: 80 - 70%• D: 70 - 60%• F: below 60%• Expect class average to be around B- / C+• Curving will only help youAmirtharajah/Parkhurst, EEC 118 Spring 2010 7Weighting• Labs 15%• Design Project 15%• Weekly Homework 5%Scale for each problem: 0 = poor effort, 1 = close, but fundamental problem, 2 = correct• Quizzes 10%Four throughout the quarter (approx. every other week), lowest score dropped (April 12, April 26, May 19, May 26)• Midterm 20%Monday, May 3, in class• Final 35%Tuesday, June 8, 1:00 - 3:00 PMCumulative, but emphasizes material after midtermAmirtharajah/Parkhurst, EEC 118 Spring 2010 8Labs and CAD Software Usage• Need to know/learn SPICE – Circuit Simulation• Use same breadboard as EEC 180A• No unsupervised lab hours!– TA or instructor must be present for your safety and security of the lab equipment– Extra lab hours will be added only in unusual circumstancesAmirtharajah/Parkhurst, EEC 118 Spring 2010 9Education Demand for Circuit Design• Industry needs circuit designers– Not just logic designers• Must understand operation at transistor level– Not just digital designers• Must understand analog effects– Not just analog designers• Must be able to comprehend Deep Sub-Micron (DSM) effects (<0.13um)• Fundamental circuit knowledge critical– Similar techniques for bipolar transistors, NMOS (even relays and vacuum tubes!)– Must be able to exploit nanoscale devices in futureAmirtharajah/Parkhurst, EEC 118 Spring 2010 10Education Demand for System Design• Industry needs system designers– Need to understand system implications of your design• Power Delivery, Clock Loading – What do you need– Need to design from the system point of view• Communication protocol – how to effectively talk with other blocks• What should be added into your block to meet system design requirements(i.e. comprehend soft block methodology for optimization of area, interconnect, etc.)You must operate at both levels!Amirtharajah/Parkhurst, EEC 118 Spring 2010 11Historical BackgroundGraph shows the growing complexity of designing integrated circuitsAmirtharajah/Parkhurst, EEC 118 Spring 2010 12Memory, Processors and Graphics• Used to be that memory and processors were the two main design drivers.http://turquoise.wpi.edu/webcourse/ch01/ch01.htmlAmirtharajah/Parkhurst, EEC 118 Spring 2010 13Memory, Processors and Graphics• We now have graphics also driving integration11010010001H96 2H96 1H97 2H97 1H98 2H98 1H99 2H99 1H00 2H00Graphics 8x/18moCPU 2x/18moFrom ISPD 1999 Keynote Speech by Chris Malachowsky of NVIDIAAmirtharajah/Parkhurst, EEC 118 Spring 2010 14Hybrid to Monolithic Trend• We continue to integrate multiple functions on a single chip– Mixture of Analog, Radio Frequency (RF), Digital– Graphics/Motherboard chipset an example of this• Cost and Performance driving market– Higher performance achieved on chip than off chip– Lower cost due to a single die versus multi-chip design– Saves on packaging, total area by eliminating redundant functions• System-on-a-Chip (SOC) conceptAmirtharajah/Parkhurst, EEC 118 Spring 2010 15What are the issues facing the industry ?• Growth of transistors is exponential• Growth of operating frequency is (was?) exponential– Reaching a limit due to power