EEC 118 Spring 2009 Homework #5Rajeevan AmirtharajahDept. of Electrical and Computer EngineeringUniversity of California, DavisIssued: April 23, 2010Due: April 30, 2010, 4 PM in 2131 Kemper.Reading: Rabaey Chapters 6.2 and 7.1-7.3 [1].Reference: Kang and Leblebici Chapters 7 and 8 [2].1 Enhancement Load Logic CircuitFigure 1: NMOS enhancement load complex gate.For the enhancement load logic gate shown in Figure 1,• Pull-up transistor W/L = 5/5• Pull-down transistors W/L = 100/5• VT 0,n= 1.0V• λ = 0.0V−11• µnCox= 100µA/V2• γ = 0.4V1/2• |2φF| = 0.6VProblem 1.1 Write a Boolean expression for the output F as a function of the inputs.Problem 1.2 Identify the worst-case input combination(s) for VOL.Problem 1.3 Calculate the worst-case value of VOL. Assume that all pull-down transistorshave the same body bias and that, initially, VOL≈ 5% of VDD= 5V.Problem 1.4 Does the value of VOLdepend on kn= µnCox? Explain why or why not.2 Two Input CMOS NOR GateProblem 2.1 Calculate VOL, VOH, VIL, VIH, NML, and NMHfor a two input CMOS NORgate. Assume for the transistors the following parameters: VT 0,n= 0.7V, VT 0,p= −0.7V,(W/L)n= 1/1, (W/L)p= 4/1, µnCox= 40 µA/V2, µpCox= 20 µA/V2. Neglect γ and λ.VDD= 5V. Assume that all inputs switch simultaneously.3 Two Input CMOS NAND GateProblem 3.1 Assume that a two input CMOS NAND gate drives a total load capacitance of0.1pF. All devices have W = 10µm, but the effective length for NMOS devices Leff= 1µmwhile for the PMOS devices Leff= 2µm. Given that k0n= 20µA/V2, k0p= 10µA/V2,VT,n= 1.0V, VT,p= −1.0V, and VDD= 5V, approximate tpLHand tpHL.4 Mixed Combinational and Sequential LogicProblem 4.1 A useful trick for highly optimized logic design is to fold a combinationalCMOS circuit into a sequential circuit such as a latch. Modify the master stage latch circuitshown in Figure 7-26 in Rabaey to incorporate the logic function F = A · (B + C). Size thetransistors such that the pullup and pulldown networks for the equivalent inverter have equalrise and fall times. Assume the mobility ratio µn/µp= 2.5, VT 0,n= |Vt0,p|, and a minimumsized device has W/L = 5/1. Write your answer in terms of the W/L ratios for the PMOSand NMOS devices. Hint: See Figure 7-31.References[1] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Per-spective, 2nd ed. Upper Saddle River, New Jersey: Prentice-Hall, Inc., 2003.[2] S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design,3rd ed. San Francisco: McGraw-Hill, Inc.,