EEC 118 Lecture #3: InvertersAnnouncementsOutlineReview: MOS Transistor StructureMOSFET Drain Current OverviewMOS Transistor SymbolsNote on MOS Transistor SymbolsInverter OperationInverter Model: Voltage Transfer CurveActual Inverter: VOH and VOLVOL and VOHNoise MarginsNoise Margins and RobustnessNoise Margin MotivationInverter Time ResponseRise and Fall TimeRing OscillatorResistive Load InverterNMOS InverterInverter as AmplifierNext Topic: CMOS InvertersEEC 118 Lecture #3:InvertersRajeevan AmirtharajahUniversity of California, DavisJeff ParkhurstIntel CorporationAmirtharajah/Parkhurst, EEC 118 Spring 2010 3Outline• Review: MOSFET Regimes of Operation• Lecture 2: Scaling, Parasitic Capacitances• Inverter Operation: Rabaey 1.3.2, 5 (Kang & Leblebici, 5.1-5.3 and 6.1-6.2)Amirtharajah/Parkhurst, EEC 118 Spring 2010 4Review: MOS Transistor StructureLWtoxxd• Important transistor physical characteristics– Channel length L = LD–2xd(K&L L = Lgate – 2LD)– Channel width W– Thickness of oxide toxAmirtharajah/Parkhurst, EEC 118 Spring 2010 5MOSFET Drain Current OverviewLinear (Triode, Ohmic):“Classical” MOSFET model, will discuss deep submicron modifications as necessary (Rabaey, Eqs. 3.25, 3.29)()()DSTGSoxDVVVLWCIλμ+−= 122Saturation:()⎟⎟⎠⎞⎜⎜⎝⎛−−=22DSDSTGSoxDVVVVLWCIμCutoff:0≈DIAmirtharajah/Parkhurst, EEC 118 Spring 2010 6MOS Transistor SymbolsNMOSPMOSDSBGDSBGDSBGDSBGDBSGDBSGAmirtharajah/Parkhurst, EEC 118 Spring 2010 7• All symbols appear in literature– Symbols with arrows are conventional in analog papers– PMOS with a bubble on the gate is conventional in digital circuits papers• Sometimes bulk terminal is ignored – implicitly connected to source or appropriate supply rail:• Unlike physical bipolar devices, source and drain are usually symmetricNote on MOS Transistor SymbolsNMOSPMOSAmirtharajah/Parkhurst, EEC 118 Spring 2010 8• Inverter is simplest digital logic gate (1 input, 1 output)• Many different circuit styles possible– Resistive-load– NMOS and Pseudo-NMOS–CMOS• Important static and dynamic characteristics– Speed (delay through the gate)– Power consumption– Robustness (tolerance to noise)– Area and process costInverter Operation‘0’ ‘1’‘1’ ‘0’In Out0 11 0Amirtharajah/Parkhurst, EEC 118 Spring 2010 9InverterVin VoutVddVddVinVoutidealactualIdeal digital inverter:Inverter Model: Voltage Transfer Curve– When Vin=0, Vout=Vdd– When Vin=Vdd, Vout=0– Infinitely sharp transition region at inverter switching thresholdVoltage transfer curve (VTC): plot of output voltage Vout vs. input voltage Vin0 VAmirtharajah/Parkhurst, EEC 118 Spring 2010 10Actual Inverter: VOHand VOL• VOHand VOLrepresent the “high” and “low” output voltages of the inverter• VOH= output voltage when Vin = ‘0’ (VOutput High)• VOL= output voltage when Vin = ‘1’ (V Output Low)• Ideally,–VOH= Vdd–VOL= 0 VVddVinVoutVOHVOL0 VAmirtharajah/Parkhurst, EEC 118 Spring 2010 11VOL and VOH• In transfer function terms:–VOL= f(VOH)–VOH= f(VOL)– f = inverter transfer function• Difference (VOH-VOL) is the voltage swing of the gate– Full-swing logic swings from ground to Vdd– Other families with smaller swingsVddVinVoutVOHVOLVOLVOHAmirtharajah/Parkhurst, EEC 118 Spring 2010 12Inverter Switching ThresholdInverter switching threshold:– Point where voltage transfer curve intersects line Vout=Vin– Represents the point at which the inverter switches state– Normally, VM≈ Vdd/2– Sometimes other thresholds desirableVddVinVoutVOHVOLVout=VinVM(K&L VTH= VM)Amirtharajah/Parkhurst, EEC 118 Spring 2010 13Noise Margins• VILand VIHmeasure effect of input voltage on inverter output• VIL= largest input voltage recognized as logic ‘0’• VIH= smallest input voltage recognized as logic ‘1’• Defined as point on VTC where slope = -1VddVinVoutVOHVOLVILVIHSlope = -1Amirtharajah/Parkhurst, EEC 118 Spring 2010 14Noise Margins and RobustnessVOHVOLVIHVIL“1”NMHNML• Noise margin is a measure of the robustness of an inverter–NML= VIL-VOL–NMH= VOH-VIH• Models a chain of inverters. Example:– First inverter output is VOH– Second inverter recognizes input > VIHas logic ‘1’– Difference VOH-VIHis “safety zone” for noiseIdeally, noise margin should be as large as possible“0”Noisy interconnectAmirtharajah/Parkhurst, EEC 118 Spring 2010 15Noise Margin Motivation• Why are VIL, VIHdefined as unity-gain point on VTC curve?– Assume there is noise on input voltage Vin()noiseinoutVVfV+=()noiseinoutinoutVdVdVVfV +=– First-order Taylor series approximation:–If gain (dVout/dVin) > 1, noise will be amplified.– If gain < 1, noise is filtered. Therefore VIL, VIHdefine regions where gain < 1Amirtharajah/Parkhurst, EEC 118 Spring 2010 16Inverter Time Response• Propagation delay measured from 50% point of Vin to 50% point of Vout• tphl= t1-t0, tplh= t3-t2, tp= ½(tphl+tplh)VddVssVdd/2VddVssVdd/2Voutt0t1t2t3VinAmirtharajah/Parkhurst, EEC 118 Spring 2010 17tRRise and Fall Time• Fall time: measured from 90% point to 10% point–tF= t1-t0• Rise time: measured from 10% point to 90% point–tR= t3-t2• Alternately, can define 20%-80% rise/fall timeV90%V10%t2t3t0t1tFAmirtharajah/Parkhurst, EEC 118 Spring 2010 18Ring Oscillator• Ring oscillator circuit: standard method of comparing delay from one process to another• Odd-number n of inverters connected in chain: oscillates with period T (usually n >> 5)V1V3V2VOHTV50%tPHL2tPLH3tPHL1tPLH2tPHL3tPLH1CloadCloadV1V2V3nftntTfntTttttttTpppphlplhphlplhphlplh21 ,211 ,2332211====++++++=LAmirtharajah/Parkhurst, EEC 118 Spring 2010 19Resistive Load Inverter• Resistor pulls up to Vdd (VOH), NMOS pulls down (VOL)LCoutVinVLRAmirtharajah/Parkhurst, EEC 118 Spring 2010 20NMOS InverterLC• Depletion NMOS always on, sourcing static currentoutVinVAmirtharajah/Parkhurst, EEC 118 Spring 2010 21Inverter as Amplifier• For Vinbetween VILand VIH, inverter gain > 1• Acts as a linear amplifier (often very high gain)• Logic levels ‘0’ and ‘1’correspond to saturating amplifier output (output is pegged to high or low supply)• Resistive load inverter same circuit as common source amplifierVddVinVoutVOHVOLVILVIHHigh gainregionAmirtharajah/Parkhurst, EEC 118 Spring 2010 22Next Topic: CMOS Inverters • CMOS Inverters– DC Characteristics: Sizing– AC Characteristics: Designing for