EEC 118 Spring 2010 Homework #1Rajeevan AmirtharajahDept. of Electrical and Computer EngineeringUniversity of California, DavisIssued: March 29, 2010Due: April 2, 2010, 4 PM in 2131 Kemper.Reading: Rabaey, Chapters 1 and 3 [1].Reference: Kang and Leblebici, Chapters 1 and 3 [2].1 IC TrendsProblem 1.1 Moore’s Law for Microprocessors. Figure 1 shows an updated plot oftransistor count for microprocessors [3]. Based on the evolutionary trends described in Chap-ter 1 of Rabaey, predict the integration complexity and the clock speed of a microprocessorin the years 2010, 2015, and 2020.Problem 1.2 Moore’s Law for DRAM. Determine also how much DRAM should beavailable on a single chip at those points in time, if Moore’s law would still hold.2 Quality MetricsProblem 2.1 Metrics Priority. Consider the four quality metrics described in Chapter1: cost, functionality and robustness, performance, and power. If you were managing an ICdesign team, how would you rank these metrics from most important to least important foryour product? Justify your answer.3 MOS TransistorProblem 3.1 Threshold Voltage. While the threshold voltage parameter VT 0is typicallydetermined empirically, a simple analytical model can be developed for it [2]:VT 0= φGC− 2φF−QB0Cox−QoxCox(1)where QB0is the depletion region charge density surface inversion (φs= −φF):1Figure 1: Moore’s Law [3].2QB0= −q2qNASi| − 2φF| (2)Note the change in sign compared to Equation 3.17 on p. 90 in Rabaey [1].Consider an MOS system with the following parameters:• tox= 200˚A• φGC= −0.85V• −2φF= 0.6V• NA= 2 × 1015cm−3• Qox= q2 × 1011C/cm2Determine the threshold voltage parameter VT 0under zero bias at rooom temperature(T = 300K) given that ox= 3.970and Si= 11.70.Problem 3.2 Channel Implant. The amount of change in the threshold voltage resultingfrom extra dopants implanted in the channel can be approximated byqNICox, where NI[cm−2]is the density of implanted impurities. Determine the type (p-type or n-type) and amountof channel implant to change the threshold voltage to 0.8V.Problem 3.3 Channel Length. Describe the relationship between the drawn channellength Ldand the electrical channel length L. Are they identical? If not, how would youexpress L in terms of Ldand other device parameters?Problem 3.4 Biasing. Draw and label an NMOS and PMOS transistor with source, drain,and gate terminals clearly labeled S, D, and G respectively. Assume VSB= 0V. Find themode of operation (cutoff, linear, or saturation) and drain current IDfor each of the appliedbiases given below. Assume for the NMOS that VT 0= 1V, W/L = 4/1, γ = 0.35V1/2,λ = 0.05 V−1, µCox= 350 µA/V2, and −2ΦF= 0.6 V. Assume identical parameters forthe PMOS except VT 0= −1V and µCox= 150 µA/V2. Ignore velocity saturation andsubthreshold conduction.1. NMOS: VGS= 1.8V, VDS= 1.8V; PMOS: VGS= −1.1V, VDS= −50mV2. NMOS: VGS= 0.9V, VDS= 1.8V; PMOS: VGS= −2.5V, VDS= −1V3. NMOS: VGS= 1.5V, VDS= 0.4V; PMOS: VGS= −1.8V, VDS= −1.6VReferences[1] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Per-spective, 2nd ed. Upper Saddle River, New Jersey: Prentice-Hall, Inc., 2003.[2] S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design,3rd ed. San Francisco: McGraw-Hill, Inc., 2003.[3] (2010, March) Moore’s law. Wikimedia Foundation, Inc. [Online].