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UCD EEC 118 - Simulating D Flip-Flops

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EEC 118 Spring 2006 Lab #3 Part 1:Simulating D Flip-FlopsDept. of Electrical and Computer EngineeringUniversity of California, DavisApril 12, 2006Reading: Kang and Leblebici Chapters 4, 5, and 8 [1].Simulation: This lab requires extensive use of HSPICE. For information on running HSPICEon the UCD ECE department network, follow this URL:http://www.ece.ucdavis.edu/cad/hspice/index.html.If you want to use another version of Spice (e.g. PSpice, Berkeley Spice, Spectre), you mustget permission f rom the instructor first.Device Models: This lab relies on freeware models from the Berkeley Device Group [2, 3].Download the model file 130nmnominal.sp from the course web site and include it in yourSpice deck.I OBJECTIVEThe objective of this experiment is to g ain experience with Hspice by simulating the VoltageTransfer Characteristic (VTC) of a CMOS inverter and to build and simulate CMOS circuitsfor sequential elements.II PRELABProblem 1 (10 points) Draw a circuit schematic for a CMOS inverter, labeling the inputin and the output out. Download and edit the spice deck template lab3pt1.sp from thecourse web page to implement the inverter. You may use the template for the inverter macroif you need to instantiate the inverter multiple times for this lab. Choose a width for thePMOS and NMOS to yield VT H= VDD/2 for the inverter, based on what you typicallyassume for carrier mobilities µnand µp. Be sure to include tha source/drain area andperimeter junction capacitances in your code. Use the layout for a minimum size transistorin Figure 1 as a guide. λ equals 65 nm for a 13 0 nm process and VDD= 1.2V.1L ≥ 2λλλλ2λλλλ2λλλλ1.5λλλλ2λλλλ1.5λλλλ1.5λλλλW ≥5λλλλFigure 1: Minimum sized transistor layout with minimum length L and width W labeled.III VOLTAGE TRANSFER CHARACTERISTICPart 1 (20 points) Simulate the Voltage Transfer Characteristic for the inverter you designfrom the Prelab, using a DC sweep analysis for vin, the inverter input volta ge. Confirm thatVT H= VDD/2, as specified in the Prelab. If it doesn’t, adjust the transistor widths until thedesign satisfies the specification. Record the device W/L ratios for your lab repor t. Turnin a plot of the VTC from your simulation, with VT Hlabeled, along with a printout of yourHspice code.Part 2 (20 points) Resize the transistors in your inverter to achieve VT H= 0.4VDDandVT H= 0.6VDD. Record the device W/L ratios for your la b report. Turn in a plot of thetwo additional VTCs from your simulatio n, with VT Hlabeled, along with a printout of yourHspice code.IV DYNAMIC MOS FLIP-FLOPPart 3 (10 points) The dynamic D Flip-Flop configuration shown in Figure 2 is often usedin high speed digital circuits to store data. Implement the circuit in Hspice using the inverterwith VT H= VDD/2 designed above in Step 1. Use the 130 nm transistor models from above,VDD= 1.2V, and C0= C1= 1 fF for the capacitors. Try to minimize the total area of thetransmission gate transistors in your implementation.Part 4 (20 points) Verify the operation of the flip-flop by wiring theQ output to the inputD. In this configuration, the flip-flop acts as a T flip-flop, and the output Q will be the clockdivided by 2. To a ccurately simulate the flip-flop under realistic lo ading conditions, connectthe inputs of 4 inverters to each of the Q andQ flip-flop outputs. This loading conditionis called a fanout of four (FO4) and is often used as a standard load to measure transientparameters such a s rise a nd fa ll times. Also, make sure that both the Clk and Clk inputsare driven by inverters instead of voltage sources, to accurately reflect the output impedanceof a realistic clock buffer. Simulate the flip-flop with a clock frequency of 1 GHz. Turn in2DQClkClkClkClkI0 I10C1CI2QFigure 2: Dynamic D Flip-Flop with Complementary Outputs.a plot of 1 0 clock cycles showing your flip-flop operating correctly, along with your Hspicecode.Part 5 (20 points) Increase the size of t he internal load capacitances from 1 fF to 10 fFand 25 fF. How does increasing the capacitances affect the output voltage levels and timing?What are the advantages and disadvantages of increasing the capacitance? Turn in a plotof 10 clock cycles showing the flip-flop operation for these two values of capacitance, alongwith your Hspice code.References[1] S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design,3rd ed. San Francisco: McGraw-Hill, Inc., 2003.[2] Device Group at UC Berkeley. (2002, July) Predictive technology model: Mosfet.download.html. [Online]. Available: ht tp://www-device.eecs.b erkeley.edu/ ptm/[3] Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, “New par adigm of predictiveMOSFET a nd interconnect modeling for early circuit design,” in Proc. of the IEEECICC, June 2000, pp.


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