EEC 118 Spring 2006 Lab #2:CMOS Inverter and GatesDept. of Electrical and Computer EngineeringUniversity of Californi a, DavisApril 2, 2006Reading: Kang and Leblebici Chapter 5, Section 7.3 [1].I OBJECTIVEThe objective of this experiment is to determine the Voltage Transfer Characteristic (VTC)of a CMOS inverter and to observe its characteristics in circuit connections.II PRELABFigure 1: CMOS inverter wiring diagra m.1Problem 1 (10 points) Use your transistor data from Lab #1 to calculate at least tenpoints on the VTC, including VOH, VIH, VOL, and VIL, for the CMOS inverter shown inFigure 1.HINT: For simplicity in hand calculations, take output voltage as the independent parameter;calculate IDand input voltage from it.III VOLTAGE TRANSFER CHARACTERISTICPart 1 (20 points) Wire up the CMOS inverter shown in Figure 1 and observe its VTC.Measure the same ten points you computed in the Prelab. Compare with your calculatedresults from the Prelab.Part 2 (20 points) Wire up a 2 input CMOS NOR g ate using the transistors in the 4007package. (a) Show the schematic in your lab report (be sure to label the pins). Verify theNOR gate truth table. (b) Connect t he two inputs together. Measure the VTC o f thisinverter. How does the VTC for this inverter-connected NOR gate differ from the inverterin Fig ure 1? Explain any observed differences.IV GATE CONNECTION-RING OSCILLATORFigure 2: Connections for NOR gate ring oscillator.Part 3 (10 points) The ring oscillator configuration shown in Figure 2 is often used tomeasure the average propagation delay time. Derive a formula which relates the averagedelay time to the period of the waveform observed at the output of any of the gates in theoscillator.Part 4 (20 points) Wire up 5 CD4 001 CMOS NOR gates to form a ring oscillator as shownin Figure 2. Use the oscilloscope to measure its oscillation frequency at supply voltages of5, 7.5, 10, 12.5, and 15 V. Also measure the current IDDdrawn from the supply at eachvoltage. From your results, calculate the average propagation delay per gate, tp, at each o fthese voltages. Explain t he tpvs. VDDtrend. Also compute the gate power-delay productat each voltage ( gate power dissipation X tp). Explain its variation with VDD.2Part 5 (20 points) Load each of the five o utput nodes of your ring oscillator with thesame capacitance value of 50 pF . Measure the oscillation frequency at VDD= 10 V. Assumethat propagation delay is a linear function of total capacitance at the o utput node of a gate(a good assumption), and calculate the approximate equiva lent capacitance (due t o internalnodes, package, and external wiring) present at the output of each ga t e with no capacitorsadded.References[1] S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design,3rd ed. San Fra ncisco: McGraw-Hill, Inc.,