EEC 118 Lecture #7: CMOS LogicAnnouncementsOutlineReview: Logic Circuit DelayReview: Inverter DelaysInverter Power ConsumptionStatic CMOSDual NetworksNAND GateNOR GateAnalysis of CMOS GatesCMOS Gates: Equivalent InverterExample: Complex GateExample: Complex GateExample: Complex GateExample: Complex GateCMOS Gate DesignAnalysis of CMOS gatesEquivalent InverterStatic CMOS Logic CharacteristicsEquivalent Inverter: VTHEquivalent Inverter: DelayExample: NOR gateExample: Complex GateTransistor SizingCommon CMOS Gate TopologiesGraph-Based Dual NetworkNext Time: More Combinational LogicEEC 118 Lecture #7:CMOS LogicRajeevan AmirtharajahUniversity of California, DavisJeff ParkhurstIntel CorporationAmirtharajah/Parkhurst, EEC 118 Spring 2010 2Announcements• Hspice documentation (html and pdf): /pkg/avanti/current/docs• Lab 3, Part 1 reports due this week at lab section• HW 4 due this Friday at 4 PM in box, Kemper 2131Amirtharajah/Parkhurst, EEC 118 Spring 2010 3Outline• Review: CMOS Inverter Transient Characteristics• Inverter Power Consumption • Combinational MOS Logic Circuits: Rabaey 6.1-6.2 (Kang & Leblebici, 7.1-7.4)Amirtharajah/Parkhurst, EEC 118 Spring 2010 4Review: Logic Circuit Delay• For CMOS (or almost all logic circuit families), only one fundamental equation necessary to determine delay:• Consider the discretized version:• Rewrite to solve for delay:• Only three ways to make faster logic: C, ΔV, IdtdVCI =tVCIΔΔ=IVCtΔ=ΔAmirtharajah/Parkhurst, EEC 118 Spring 2010 5Review: Inverter Delays⎥⎦⎤⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛−+−+−−= 1)(4ln2)(,0,0,0,0 OLOHnTOHnTOHnTnTOHnLPHLVVVVVVVVVkCt⎥⎥⎦⎤⎢⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛−+−−+−−−−= 1)(4ln2)(,0,0,0,0OLOHpTOLOHpTOLOHpTpTOLOHpLPLHVVVVVVVVVVVVkCt• High-to-low and low-to-high transitions (exact):• Similar exact method to find rise and fall times• Note: to balance rise and fall delays (assuming VOH= VDD, VOL= 0V, and VT0,n=VT0,p) requires5.2≈=⎟⎠⎞⎜⎝⎛⎟⎠⎞⎜⎝⎛pnnpLWLWμμ1=npkkAmirtharajah/Parkhurst, EEC 118 Spring 2010 6Inverter Power Consumption• Static power consumption (ideal) = 0– Actually DIBL (Drain-Induced Barrier Lowering), gate leakage, junction leakage are still present• Dynamic power consumptionfVCVCTPDDloadDDloadavg221==()⎥⎦⎤⎢⎣⎡⎟⎠⎞⎜⎝⎛−+⎟⎠⎞⎜⎝⎛−=∫∫2/02/1TTToutloadoutDDoutloadoutavgdtdtdVCVVdtdtdVCVTP⎥⎥⎦⎤⎢⎢⎣⎡⎟⎠⎞⎜⎝⎛−+⎟⎟⎠⎞⎜⎜⎝⎛−=TToutloadloadoutDDToutloadavgVCCVVVCTP2/22/022121()()∫=TavgdttitvTP01Amirtharajah/Parkhurst, EEC 118 Spring 2010 7Static CMOS• Complementary pullupnetwork (PUN) and pulldownnetwork (PDN)• Only one network is on at a time• PUN: PMOS devices–Why?• PDN: NMOS devices–Why?• PUN and PDN are dual networksPUNPDNFABCABCAmirtharajah/Parkhurst, EEC 118 Spring 2010 8Dual NetworksBAF• Dual networks: parallel connection in PDN = series connection in PUN, vice-versa• If CMOS gate implements logic function F:– PUN implements function F– PDN implements function G = FExample: NAND gateparallelseriesAmirtharajah/Parkhurst, EEC 118 Spring 2010 9NAND Gate• NAND function: F = A•B• PUN function: F = A•B = A + B– “Or” function (+) → parallel connection– Inverted inputs A, B → PMOS transistors• PDN function: G = F = A•B – “And” function (•) → series connection– Non-inverted inputs → NMOS transistorsAmirtharajah/Parkhurst, EEC 118 Spring 2010 10• PDN: G = F = A+B• PUN: F = A+B = A•B• NOR gate operation: F = A+BNOR GateABABAmirtharajah/Parkhurst, EEC 118 Spring 2010 11Analysis of CMOS Gates• Represent “on” transistors as resistors111RWWWRR• Transistors in series → resistances in series• Effective resistance = 2R• Effective length = 2LAmirtharajah/Parkhurst, EEC 118 Spring 2010 12Analysis of CMOS Gates (cont.)• Represent “on” transistors as resistors000RWWWRR• Transistors in parallel → resistances in parallel• Effective resistance = ½ R• Effective width = 2WAmirtharajah/Parkhurst, EEC 118 Spring 2010 13CMOS Gates: Equivalent Inverter• Represent complex gate as inverter for delay estimation• Typically use worst-case delays• Example: NAND gate– Worst-case (slowest) pull-up: only 1 PMOS “on”– Pull-down: both NMOS “on”WNWNWPWPWP½WNAmirtharajah/Parkhurst, EEC 118 Spring 2010 14Example: Complex GateDesign CMOS gate for this truth table:ABCF00010011010101111001101011001110F = A•(B+C)Amirtharajah/Parkhurst, EEC 118 Spring 2010 15AExample: Complex GateDesign CMOS gate for this logic function:F = A•(B+C) = A + B•C1. Find NMOS pulldown network diagram:G = F = A•(B+C)CBNot a unique solution: can exchange order of series connectionAmirtharajah/Parkhurst, EEC 118 Spring 2010 16Example: Complex Gate2. Find PMOS pullup network diagram: F = A+(B•C)Not a unique solution: can exchange order of series connection (B and C inputs)CBAFAmirtharajah/Parkhurst, EEC 118 Spring 2010 17CBACBAWPWPWPWNWNCompleted gate:WNExample: Complex GateF• What is worse-case pullup delay?• What is worse-case pulldown delay?• Effective inverter for delay calculation: ½WP½WNAmirtharajah/Parkhurst, EEC 118 Spring 2010 18CMOS Gate Design• Designing a CMOS gate:– Find pulldown NMOS network from logic function or by inspection– Find pullup PMOS network• By inspection• Using logic function• Using dual network approach– Size transistors using equivalent inverter• Find worst-case pullup and pulldown paths• Size to meet rise/fall or threshold requirementsAmirtharajah/Parkhurst, EEC 118 Spring 2010 19Analysis of CMOS gates• Represent “on” transistors as resistors111RWWWRR• Transistors in series → resistances in series• Effective resistance = 2R• Effective width = ½ W (equivalent to 2L)• Typically use minimum length devices (L = Lmin)Amirtharajah/Parkhurst, EEC 118 Spring 2010 20Analysis of CMOS Gates (cont.)• Represent “on” transistors as resistors000RWWWRR• Transistors in parallel → resistances in parallel• Effective resistance = ½ R• Effective width = 2W• Typically use minimum length devices (L = Lmin)Amirtharajah/Parkhurst, EEC 118 Spring 2010 21Equivalent Inverter• CMOS gates: many paths to Vdd and Gnd– Multiple values for VTH, VIL, VIH, etc– Different delays for each input combination• Equivalent inverter– Represent each gate as an inverter with appropriate device width– Include only