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UCD EEC 118 - Homework 2

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EEC 118 Spring 2010 Homework #2Rajeevan AmirtharajahDept. of Electrical and Computer EngineeringUniversity of California, DavisIssued: April 2, 2010Due: April 9, 2010, 4 PM in 2131 Kemper.Reading: Rabaey, Chapters 3 and 5 [1].Reference: Kang and Leblebici, Chapters 3 and 5 [2].1 FET CapacitancesAn NMOS transistor is fabricated with the following physical dimensions and dopant con-centrations:• tox= 200˚A• W = 10µm• Ld= 1.5µm• xd= 0.25µm• LS= 5µm• xj= 0.4µm• ND= 1020cm−3• Substrate Doping NA= 1016cm−3• Channel Stop Implant Doping N+A= 1019cm−3Problem 1.1 Determine the drain diffusion capacitance for VDB= 5V and 2.5V.Problem 1.2 Calculate the overlap capacitance between gate and drain.1Figure 1: NMOS enhancement load inverter.2 Enhancement Load InverterConsider the NMOS inverter circuit shown in Figure 1 which consists of two enhancement-mode NMOS transistors with the following parameters: VT 0= 0.8V, W/L ratios as shownin the figure, γ = 0.38V1/2, λ = 0.0V−1, µCox= 45µA/V2, −2ΦF= 0.6V, and VDD= 5V.Problem 2.1 Calculate values for VOHand VOL. Note that the substrate-bias effect foreither or both devices must be taken into consideration.Problem 2.2 Interpret your results for Problem 2.1 in terms of noise margins and static(DC) power dissipation.Problem 2.3 Calculate the steady-state current which is drawn from the DC power supplywhen the input is a logic “1”, i.e. when Vin= VOH.3 CMOS InverterConsider a CMOS inverter with the following transistor parameters:• NMOS: VT 0= 0.6V, W/L = 8, λ = 0.0V−1, µCox= 60µA/V2• PMOS: VT 0= −0.7V, W/L = 12, λ = 0.0V−1, µCox= 25µA/V2Assume VDD= 3.3V.Problem 3.1 Calculate the noise margins and the switching threshold (VM) of this circuit.Problem 3.2 For this problem and the next, assume the channel length of both transistorsis 0.8µm. Determine the WP/WNratio so that the switching threshold of the inverter isVM= 1.4V.2Problem 3.3 The CMOS fabrication process used to manufacture this inverter allows avariation in the NMOS threshold voltage VT 0,nof ±15% around its nominal value of 0.6V,and a variation in the PMOS threshold voltage VT 0,pof ±20% around its nominal value of-0.7V. Assuming that all other device parameters always retain their nominal values, findthe upper and lower limits of the switching threshold VMof the circuit you designed inProblem 3.2.4 CMOS Inverter in FeedbackFigure 2: CMOS inverter in feedback configuration with NMOS device M3.Consider the CMOS inverter you designed in Problem 3.2, with the circuit configurationshown in Figure 2.Problem 4.1 Calculate the output voltage level Vout.Problem 4.2 Determine if the process-related variation of VT 0,nof transistor M3 has anyinfluence on the output voltage Vout.Problem 4.3 Calculate the total current being drawn from the power supply source, anddetermine its variation due to process-related threshold voltage variations.References[1] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Per-spective, 2nd ed. Upper Saddle River, New Jersey: Prentice-Hall, Inc., 2003.[2] S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design,3rd ed. San Francisco: McGraw-Hill, Inc.,


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