EEC 118 Spring 2010 Homework #4Rajeevan Amirt harajahDept. of E lectrical and Com puter EngineeringUniversity of Cal ifornia , DavisIssued: April 16, 2010Due: April 23 , 2010, 4 PM in 2131 Kemper.Reading: Rabaey Chapter 5 [1].Reference: Kang and Leblebici Chapter 6 [2].1 CMOS InverterConsider a CMOS inverter with the following device parameters for the transistors:• NMOS: VT 0= 0.8V, L = 1.0µm, λ = 0.0V−1, µCox= 50µA/V2• PMOS: VT 0= −1.0V, L = 1.0µm, λ = 0.0V−1, µCox= 20µA/V2and assume the power supply voltage VDDis 5.0V. The total output load capacitance ofthis circuit is Cout= 2pF, which is independent of transistor dimensions.Problem 1.1 Sizing. Determine the channel width of the NMOS and PMOS transistorssuch that the switching threshold voltage VMis equal to 2.2V and the output rise timetr= 5ns.Problem 1.2 Delay. Calculate the average propagation delay time tpdfor the circuit de-signed in Problem 1.1.Problem 1.3 VDDVariation. How do the switching threshold VMand the delay timeschange if the power supply voltage is dropped from 5V t o 3.3V? Provide an interpretationof the results.2 CMOS InverterConsider a CMOS inverter with the same process parameters as in Problem 1. The switchingthreshold is designed to be equal to 2.4V. A simplified expression of the total output loadcapacitance is given as:1Cout= 500 + Cdb,n+ Cdb,pCdb,n= (100 + 9Wn)Cdb,p= (80 + 7Wp)where Cout, Cdb,n, and Cdb,pall have units of f F and Wnand Wpare expressed in microns.Problem 2.1 Sizing. Determine the width of both transistors such that the propagationdelay tpHLis smaller than 0.825ns.Problem 2.2 Rise and Fall Times. Assume now that the CMOS inverter has beendesigned with dimensions (W/L)n= 6 and (W/L)p= 15, and that the total output loadcapacitance is 250fF. Calculate the output rise and fall time by computing the averagecurrent.3 CMOS InverterConsider a CMOS inverter with the following device parameters for the transistors:• NMOS: VT 0= 1.0V, W/L = 10, λ = 0.0V−1, µCox= 45µA/V2• PMOS: VT 0= −1.2V, W/L = 20, λ = 0.0V−1, µCox= 25µA/V2and assume the power supply voltage VDDis 5.0 V with a total output load capacitanceof this circuit Cout= 1.5pF.Problem 3.1 Rise and Fall Times. Calculate the r ise and f all time of the output signalusing (1) an exact method (differential equations) and (2) an approximate method (averagecurrent).Problem 3.2 Frequency. Determine the maximum frequency of a periodic square-waveinput signal so that the output voltage can still exhibit a full logic swing f r om 0V to 5V ineach cycle.Problem 3.3 Power. Calculate the dynamic power dissipation at this frequency.Problem 3.4 Redesign. Assume the output load capacitance is mainly dominated byfixed fan-out components (which are independent of Wnand Wp). We want to re-design theinverter so that the propagation delay times are reduced by 25%. Determine the requiredchannel dimensions of the NMOS and PMOS transistors. How does this re-design influencethe switching (inversion) threshold VM?References[1] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Per-spective, 2nd ed. Upper Saddle River, New Jersey: Prentice-Hall, Inc., 2003.[2] S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design,3rd ed. San Francisco: McGraw-Hill, Inc.,