EEC 118 Lecture #16: ManufacturabilityAnnouncementsOutlineDesign for ManufacturabilityCircuit Parameter VariationsCMOS Inverter ExamplePerformance Variation ExampleYield Estimation and MaximizationWorst-Case Design 1Worst-Case Design 2SummaryNext Topic: Future Directions & Final ReviewEEC 118 Lecture #16:ManufacturabilityRajeevan AmirtharajahUniversity of California, DavisAmirtharajah, EEC 118 Spring 2010 3Outline• Finish interconnect discussion• Manufacturability: Rabaey G, H (Kang & Leblebici, 14)Amirtharajah, EEC 118 Spring 2010 4Design for Manufacturability• For class projects or university research, goal is a single working circuit or small number of prototypes– Similar scale for industrial research projects• Production goal is usually thousands to 100s of millions of working (or at least marketable) parts– Must evaluate circuit designs over a range of parameter variations to ensure correct functionality, performance• Design for Manufacturabilityor Statistical Circuit Design encompasses a variety of techniques– Yield estimation and maximization, worst-case analysis, etc.Amirtharajah, EEC 118 Spring 2010 5Circuit Parameter Variations• All circuit parameters vary some amount due to variations in process, lithography, or environment– Geometric parameters: transistor W and L– Device parameters: VT, tox, μ– Interconnect parameters: R, C– Operating conditions: VDD, T• Variations occur both spatially and temporally– Circuit-to-circuit on same die (spatial)– Die-to-die on same wafer (spatial)– Wafer-to-wafer in same fab (temporal)• Example: transistor width W = W0+ ΔWIncreasing variationDesigner controls RandomAmirtharajah, EEC 118 Spring 2010 6• For both NMOS and PMOS:–W = W0+ ΔW–L = L0+ ΔL–VT= VT0+ ΔVT–k’= k’0+ Δk’• For capacitor:–Cload= C0+ ΔC• For entire circuit:–T = T0+ ΔT–VDD= VDD0+ ΔVDD• All these parameters affect circuit performance!CMOS Inverter ExampleVinVoutCloadAmirtharajah, EEC 118 Spring 2010 7Inverter Delay Histogram05101520250-10 10-20 20-30 30-40 40-50 50-60 60-70 70-80 80-90 90-100Propagation Delay (ps)Count• Delay variations with parameters, loading, VDD, and TPerformance Variation ExampleAmirtharajah, EEC 118 Spring 2010 8Yield Estimation and Maximization• Parametric Yield: ratio of total acceptable circuits to total manufactured circuits– Design for manufacturability aims to maximize yield (and $$)• Yield statistics are usually complicated since circuit performance is complex function of parameters• Numerous methods for estimating and maximizing yield– Response surface models (RSM): compact analytical model fit to circuit simulations using Design of Experiments– Direct Monte Carlo circuit simulations or the RSM can be used to estimate yields– Designer controlled parameters then adjusted to maximize yield estimatesAmirtharajah, EEC 118 Spring 2010 9Worst-Case Design 1• Given range of variations for process, voltage, temperature identify worst (best) cases for performance parameter of interest– Process corner models from fab define limits of device performance– Labeled by NMOS-PMOS pairs, e.g. Typical NMOS-Typical PMOS (TT)– Usual additional corners: Fast NMOS-Fast PMOS (FF), Slow NMOS-Slow PMOS (SS), Fast NMOS-Slow PMOS (FS), Slow NMOS-Fast PMOS (SF)– Usual voltage corners: Nominal VDD+/- 10% – Temperature range: 0 – 100 oCAmirtharajah, EEC 118 Spring 2010 10Worst-Case Design 2• Identify worst (best) cases for performance parameter of interest• Typical Speed Corner– Typical NMOS-Typical PMOS (TT), nominal VDD, room temperature 27 oC• Slow Speed Corner– Slow NMOS-Slow PMOS (SS), 0.9 x VDD, maximum temperature 100 oC• Fast Speed Corner– Fast NMOS-Fast PMOS (FF), 1.1 x VDD, minimum temperature 0 oCAmirtharajah, EEC 118 Spring 2010 11Summary• Design for manufacturability converts a prototype into a “real” design for large-scale production– Statistical models of process, device and interconnect parameters, and operating conditions used to estimate and maximize yield (and profits)– Analysis is difficult because of complexity, usually numerical models and many simulations required• Variability trend is worsening as processes shrink– For example, locations of individual dopant atoms can affect transistor performance• Statistical circuit design is becoming as important as performance and power!Amirtharajah, EEC 118 Spring 2010 12Next Topic: Future Directions & Final Review• Future directions in CMOS digital circuits• Alternative logic technologies to CMOS• Final exam