EEC 118 Lecture #15: InterconnectAnnouncementsOutlineInterconnect ModelingInterconnect Models: Regions of ApplicabilityInterconnect Models: Regions of ApplicabilityResistanceParallel-Plate CapacitanceFringing Field CapacitanceTotal Capacitance ModelTotal Capacitance ModelAlternative Total Capacitance ModelsCapacitive CouplingMiller CapacitanceData Dependent Switched Capacitance 1Data Dependent Switched Capacitance 2Lumped RC ModelRC T-ModelDistributed RC ModelRepeater Insertion to Reduce Wire Delay SummaryNext Topic: Design for ManufacturabilityEEC 118 Lecture #15:InterconnectRajeevan AmirtharajahUniversity of California, DavisAmirtharajah, EEC 118 Spring 2010 3Outline• Review and Finish: Low Power Design• Interconnect Effects: Rabaey Ch. 4 and Ch. 9 (Kang & Leblebici, 6.5-6.6)Amirtharajah, EEC 118 Spring 2010 4Interconnect Modeling• Early days of CMOS, wires could be treated as ideal for most digital applications, not so anymore!• On-chip wires have resistance, capacitance, and inductance– Similar to MOSFET charging, energy depends solely on capacitance– Resistance might impact low power adiabatic charging, static current dissipation, speed– Ignore inductance for all but highest speed designs• Interconnect modeling is whole field of research itself!Amirtharajah, EEC 118 Spring 2010 5Interconnect Models: Regions of Applicability• For highest speed applications, wire must be treated as a transmission line– Includes distributed series resistance, inductance, capacitance, and shunt conductance (RLGC) • Many applications it is sufficient to use lumped capacitance (C) or distributed series resistance-capacitance model (RC)• Valid model depends on ratio of rise/fall times to time-of-flight along wire – l: wire length– v: propagation velocity (speed of light)– l/v: time-of-flight on wireAmirtharajah, EEC 118 Spring 2010 6Interconnect Models: Regions of Applicability• Transmission line modeling (inductance significant):trise(tfall) < 2.5 x (l / v)• Either transmission line or lumped modeling:2.5 x (l / v) < trise(tfall) < 5 x (l / v)• Lumped modeling:trise(tfall) > 5 x (l / v)Amirtharajah, EEC 118 Spring 2010 7Resistance• Resistance proportional to length and inversely proportional to cross section• Depends on material constant resistivity ρ (Ω-m)tWLWLRtWLALRsq===ρρtRsqρ=Amirtharajah, EEC 118 Spring 2010 8Parallel-Plate Capacitance• Width large compared to dielectric thickness, height small compared to width: E field lines orthogonal to substratetWLWLhCrε=hsubstratedielectricAmirtharajah, EEC 118 Spring 2010 9Fringing Field Capacitance• When height comparable to width, must account for fringing field component as welltWLhsubstratedielectricAmirtharajah, EEC 118 Spring 2010 10Total Capacitance Model• When height comparable to width, must account for fringing field component as well• Model as a cylindrical conductor above substratetWhsubstratedielectricAmirtharajah, EEC 118 Spring 2010 11Total Capacitance Model• Total capacitance per unit length is parallel-plate (area) term plus fringing-field term:• Model is simple and works fairly well (Rabaey, 2nd ed.)– More sophisticated numerical models also available• Process models often give both area and fringing (also known as sidewall) capacitance numbers per unit length of wire for each interconnect layer()12log22 ++⎟⎠⎞⎜⎝⎛−=+=thtWhcccrrfringeppπεεAmirtharajah, EEC 118 Spring 2010 12Alternative Total Capacitance Models• For wide lines (w ≥ t/2) Kang & Leblebici Eq. 6.53:• For narrow lines (w ≤ t/2) Kang & Leblebici Eq. 6.54:⎟⎟⎠⎞⎜⎜⎝⎛⎟⎠⎞⎜⎝⎛++++⎟⎠⎞⎜⎝⎛−=22221ln22thththtWhCrrπεεrrrthththhthWCεπεε47.122221ln20543.01+⎟⎟⎠⎞⎜⎜⎝⎛⎟⎠⎞⎜⎝⎛+++⎟⎠⎞⎜⎝⎛−+=Amirtharajah, EEC 118 Spring 2010 13Capacitive Coupling• Fringing fields can terminate on adjacent conductors as well as substrate• Mutual capacitance between wires implies crosstalk, affects data dependency of powersubstratedielectricAmirtharajah, EEC 118 Spring 2010 14Miller Capacitance• Amount of charge moved onto mutual capacitance depends on switching of surrounding wires• When adjacent wires move in opposite direction, capacitance is effectively doubled (Miller effect)mCmCABC+−V+−V()ifmVVCQ−=Δ()()DDDDmVVC−−=DDmVC2=Amirtharajah, EEC 118 Spring 2010 15Data Dependent Switched Capacitance 1• When adjacent wires move in same direction, mutual capacitance is effectively eliminatedACBORACB0=effCACBORACBmeffCC 4=ACBORACBmeffCC 2=ACBORACBAmirtharajah, EEC 118 Spring 2010 16Data Dependent Switched Capacitance 2• When adjacent wires are static, mutual capacitance is effectively to ground• Remember: it is the charging of capacitance where we account for energy from supply, notdischarging00BOR11BmeffCC 2=10BOR01B01BOR10B11BOR00BAmirtharajah, EEC 118 Spring 2010 17Lumped RC Model• Simplest model used to represent the resistive and capacitive interconnect parasitics• Propagation delay (same as FET switch model):CRRCtPLH69.0≈Amirtharajah, EEC 118 Spring 2010 18RC T-Model• Significantly improves accuracy of transient behavior over the lumped RC model• Useful if simulation time is a bottleneck, much simpler than fully distributed modelCR/2R/2Amirtharajah, EEC 118 Spring 2010 19Distributed RC Model• Elmore delay approximation for RC ladder network:C/NR/NC/NR/N…C/NR/N2RCtDN=∞→NasAmirtharajah, EEC 118 Spring 2010 20Repeater Insertion to Reduce Wire Delay NC /NC /• Insert inverters along long wires at regular intervals• Breaks up resistance and capacitance, reducing delay dramatically12 NAmirtharajah, EEC 118 Spring 2010 21Summary• Many important effects to consider in interconnect design– Resistance, capacitance, inductance can all affect signal performance– Long rise/fall time signals, only resistance and capacitance needs to be considered• Several models useful for RC interconnect delay analysis– Simple lumped (1 R, 1 C) model: easy to analyze and/or simulate, will be pessimistic– T-model (2 Req= R/2, 1 C): more accurate than lumped– Distributed model (N Req= R/N, N Ceq= C/N): most accurate, use Elmore delay approximation for hand analysisAmirtharajah, EEC 118 Spring 2010 22Next Topic: Design for Manufacturability• Parameter variations in CMOS digital circuits• Yield maximization and worst-case