EEC 118 Lecture #2: MOSFET Structure and Basic OperationAnnouncementsOutlineMOS Transistor TypesMOS Transistor SymbolsNote on MOS Transistor SymbolsMOS Transistor StructureNMOS Transistor I-V Characteristics INMOS Transistor I-V Characteristics IIMOS Transistor Operation: CutoffMOS Transistor Operation: InversionThreshold Voltage ComponentsThreshold Voltage SummaryThreshold Voltage (NMOS vs. PMOS)Body EffectMOS Transistor Regions of OperationMOSFET Drain Current OverviewCutoff RegionLinear RegionLinear Region I/V Equation DerivationLinear Region I/V EquationSaturation RegionSaturation I/V EquationMOS I/V CharacteristicsChannel Length ModulationMOS I/V Curve SummaryMOS I/V Equations SummaryA Fourth Region: SubthresholdMOSFET Scaling EffectsShort Channel EffectsMOSFET CapacitancesOxide Capacitances: OverlapJunction CapacitanceJunction CapacitanceJunction CapacitanceJunction CapacitanceExample: Junction CapNext Topic: InvertersEEC 118 Lecture #2:MOSFET Structure and Basic OperationRajeevan AmirtharajahUniversity of California, DavisJeff ParkhurstIntel CorporationAmirtharajah/Parkhurst, EEC 118 Spring 2010 2Announcements• Lab 1 this week, report due next week• Bring your breadboards to lab!• HW 1 due this Friday at 4 PM in box, Kemper 2131• Instructor office hours this week: Wednesday 11 AM -12 PM• TA Office Hours: Thursdays 3:30-5 PM, Kemper 2157/2161Amirtharajah/Parkhurst, EEC 118 Spring 2010 3Outline• Finish Lecture 1 Slides• Switch Example• MOSFET Structure• MOSFET Regimes of Operation• Scaling• Parasitic CapacitancesAmirtharajah/Parkhurst, EEC 118 Spring 2010 4• Rabaey Ch. 3 (Kang & Leblebici Ch. 3)• Two transistor types (analogous to bipolar NPN, PNP)– NMOS: p-type substrate, n+source/drain, electrons are charge carriers– PMOS: n-type substrate, p+source/drain, holes are charge carriers MOS Transistor TypessourcedrainP-substrateN+N+NMOSsourcedrainN-substrateP+P+PMOSgate gatebulk (substrate)bulk (substrate)Amirtharajah/Parkhurst, EEC 118 Spring 2010 5MOS Transistor SymbolsNMOSPMOSDSBGDSBGDSBGDSBGDBSGDBSGAmirtharajah/Parkhurst, EEC 118 Spring 2010 6• All symbols appear in literature– Symbols with arrows are conventional in analog papers– PMOS with a bubble on the gate is conventional in digital circuits papers• Sometimes bulk terminal is ignored – implicitly connected to supply:• Unlike physical bipolar devices, source and drain are usually symmetricNote on MOS Transistor SymbolsNMOSPMOSAmirtharajah/Parkhurst, EEC 118 Spring 2010 7MOS Transistor StructureLWtoxxd• Important transistor physical characteristics– Channel length L = LD–2xd(K&L L = Lgate – 2LD)– Channel width W– Thickness of oxide toxAmirtharajah/Parkhurst, EEC 118 Spring 2010 8NMOS Transistor I-V Characteristics I• I-V curve vaguely resembles bipolar transistor curves– Quantitatively very different– Turn-on voltage called Threshold Voltage VTAmirtharajah/Parkhurst, EEC 118 Spring 2010 9NMOS Transistor I-V Characteristics II• Drain current varies quadratically with gate-source voltage VGS (in Saturation)Amirtharajah/Parkhurst, EEC 118 Spring 2010 10MOS Transistor Operation: Cutoff• Simple case: VD= VS= VB= 0– Operates as MOS capacitor (Cg = gate to channel)– Transistor in cutoff region• When VGS < VT0, depletion region forms– No carriers in channel to connect S and D (Cutoff)Vg< VT0source drainP-substrateVB= 0Vd= 0Vs = 0depletionregionAmirtharajah/Parkhurst, EEC 118 Spring 2010 11MOS Transistor Operation: Inversion• When VGS> VT0, inversion layer forms• Source and drain connected by conducting n-type layer (for NMOS)– Conducting p-type layer in PMOSsource drainP-substrateVB= 0Vg> VT0Vd= 0Vs = 0depletionregioninversionlayerAmirtharajah/Parkhurst, EEC 118 Spring 2010 121. Work function difference between gate and channel (depends on metal or polysilicon gate): ΦGC2. Gate voltage to invert surface potential: -2ΦF3. Gate voltage to offset depletion region charge: QB/Cox4. Gate voltage to offset fixed charges in the gate oxide and oxide-channel interface: Qox/CoxThreshold Voltage Components• Four physical components of the threshold voltageoxoxoxtCε=: gate oxide capacitance per unit areaAmirtharajah/Parkhurst, EEC 118 Spring 2010 13Threshold Voltage Summary• If VSB= 0 (no substrate bias):• If VSB≠ 0 (non-zero substrate bias)• Body effect (substrate-bias) coefficient:• Threshold voltage increases as VSBincreases!oxoxoxBFGCTCQCQV −−−Φ=002φ()FSBFTTVVVφφγ220−+−+=oxSiACqNεγ2=(K&L 3.20)(3.19)(K&L 3.24)Amirtharajah/Parkhurst, EEC 118 Spring 2010 14Threshold Voltage (NMOS vs. PMOS)NMOS PMOSSubstrate Fermi potentialφF< 0 φF> 0Depletion charge densityQB< 0 QB> 0Substrate bias coefficientγ > 0 γ < 0Substrate bias voltageVSB> 0 VSB< 0Amirtharajah/Parkhurst, EEC 118 Spring 2010 15VxBody Effect• Body effect: Source-bulk voltage VSBaffects threshold voltage of transistor– Body normally connected to ground for NMOS, Vdd(Vcc) for PMOS– Raising source voltage increases VTof transistor– Implications on circuit design: series stacks of devicesVT0ABIf Vx> 0, VSB(A) > 0,VT(A) > VTOAmirtharajah/Parkhurst, EEC 118 Spring 2010 16MOS Transistor Regions of Operation• Three main regions of operation• Cutoff: VGS< VTNo inversion layer formed, drain and source are isolated by depleted channel. IDS ≈ 0• Linear (Triode, Ohmic): VGS> VT, VDS< VGS-VTInversion layer connects drain and source.Current is almost linear with VDS(like a resistor)• Saturation: VGS > VT, VDS ≥ VGS-VTChannel is “pinched-off”. Current saturates (becomes independent of VDS, to first order).Amirtharajah/Parkhurst, EEC 118 Spring 2010 17MOSFET Drain Current OverviewLinear (Triode, Ohmic):“Classical” MOSFET model, will discuss deep submicron modifications as necessary (Rabaey, Eqs. 3.25, 3.29)()()DSTGSoxDVVVLWCIλμ+−= 122Saturation:()⎟⎟⎠⎞⎜⎜⎝⎛−−=22DSDSTGSoxDVVVVLWCIμCutoff:0≈DIAmirtharajah/Parkhurst, EEC 118 Spring 2010 18Cutoff Region• For NMOS: VGS< VTN• For PMOS: VGS> VTP• Depletion region – no inversion• Current between drain and source is 0– Actually there is always some leakage (subthreshold) currentsource drainsubstrateVBVGVDVSdepletionregionAmirtharajah/Parkhurst, EEC 118 Spring 2010 19Linear Region• When VGS>VT, an inversion layer forms between drain and source• Current IDSflows from drain to source (electrons travel from source to drain)• Depth of channel depends on V between gate and