MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science 6 002 Electronic Circuits Fall 2002 Quiz 2 Solutions Name Recitation Section Recitation Instructor Teaching Assistant Enter all your work and your answers directly in the spaces provided on the printed pages Make sure that your name is on all sheets Use the backs of the printed pages as scratch paper but we will only grade the work that you neatly transfer to the spaces on the printed pages Answers must be derived or explained not just simply written down The quiz is closed book but calculators are allowed This quiz contains 8 pages including the cover sheet Make sure that your quiz contains all 8 pages and that you hand in all 8 pages Problem Points Grade Grader 1 50 2 50 Total 100 Name Solutions 2 Problem 1 50 points Figure 1 a shows a simple one stage MOSFET ampli er The inputoutput relationship is graphed in Figure 1 b where the solid curve indicates operation in the saturated region and the dashed curves indicate operation in the cuto and triode regions Figure 1 Circuit and characteristic for Problem 1 A Determine the MOSFET threshold voltage VT and the power supply voltage VS VT 2V VS 12V B Determine the MOSFET parameter K vO VS RL K 2 vI VT 2 12V 103 K vI 2V 2 Using point vI 4V vO 2V 2V 12V 103 K 4V 2V 2 K 2 5mA V 2 K 2 5mA V 2 C Determine the minimum and maximum small signal gain vvoi in the saturated region A graphical solution is acceptable vo RL K vI VT 5V 1 vI 2V vi vo If vI 2 4 then 0 10 vi min vvoi 0 max vvoi 10 Name Solutions 3 The circuit shown in Figure 2 is used to bias the ampli er and inject an input signal to be ampli ed The values of R1 and R2 are to be determined Figure 2 Circuit for Problem 1 D where vO VO vo D Determine the bias voltage EI with respect to ground such that equal positive and negative excursions of vo can be as large as possible without leaving the saturation region For maximum excursions center VO in the middle of the saturation region i e VO 7V With vi 0V since it is small signal and we re computing bias conditions choose EI such that VO 7V 7V 12V 5 2V 1 EI 2V 2 EI 2 2 V 3 4V EI 3 4V E The resistors in Figure 2 satisfy the constraint R1 R2 10k Determine values for R1 and R2 so that the bias voltage EI will be that found in part D R2 R1 5V R2 R1 5V 5V R1 R2 R R2 10k 1 R2 R1 4 2 2 k EI R1 R2 10k R1 3 2 k 1 6k R2 7 2 k 8 4k R1 1 6k R2 8 4k Name Solutions 4 F Draw the small signal circuit valid for the operating point de ned in part D Label the numerical values of all circuit parameters and determine the small signal gain at this operating point from your circuit gm id iD vgs vGS 2 K EI VT vGS EI 2 5mA V 2 Gain 5 2 m 3 5m 2 V 2V 2 5 2 vo m 5 2m 7 2k v 2 v i o 5 2m 7 vi Name Solutions 5 Problem 2 50 points The circuit of Figure 3 is a model for a proposed logic inverter which is to join a logic family whose members must satisfy the following digital discipline VIH 3 3V VIL 1 55V VOH 4 0V VOL 1 0V Figure 3 Circuit for Problem 2 Switch S is controlled by the voltage vIN such that it is open when vIN 1 8V and closed otherwise Also IS 0 5mA in the current source A Fill in the following table with the output voltages which will result if the circuit is supplied by input voltages which satisfy the digital discipline Input vOU T V High 0V Low 5V If vIN vIL 1 55V then switch S is open and vOU T 0 5mA 10k 5V If vIN vIH 3 3V then switch S is closed the output terminal is shorted and vOU T 0V Name Solutions 6 B Each gate in this logic family will have the same input resistance RIN One of the requirements of this gate is that it be able to drive up to three other gates from this family connected in parallel Find the minimum allowable value of RIN Rmin such that this gate will satisfy the digital discipline under all acceptable operating con gurations The constraint is Rmin 3 10k IS VOH Rmin 120k Rmin 120k C What is the noise margin for this logic family i e what is the maximum noise amplitude in V that can appear anywhere in a circuit in which this logic family is used such that all the gates in this circuit are guaranteed to operate properly Noise margin min VIL VOL VOH VIH min 1 55V 1 0V 4 0V 3 3V min 0 55V 0 7V 0 55V Noise margin 0 55V Name Solutions 7 D Circle the logic expressions which describe the logic functions implemented by the circuits shown in Figures 4 and 5 from the respective lists below each gure The circuits employ the logic inverter of Figure 3 indicated by a rectangular box You may assume that each MOSFET has threshold voltage VT of 2 0V Figure 4 Logic circuit for Problem 2 D z xy z x y z x y z x y z y z x xy z x y z x x y x y Name Solutions 8 Figure 5 Logic circuit for Problem 2 D z xy z x y z x y z x y z y z x xy z x y z x x x y x
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