CS250 VLSI Systems Design Fall 2009 John Wawrzynek Krste Asanovic with John Lazzaro Circuit Timing Lecture 01 Introduction 1 CS250 UC Berkeley Fall 09 Circuit Delay is a Consequence of the Physics of Transistors and Interconnections As a designer you need to understand these physics enough to make appropriate design decisions Fortunately for us CMOS can be accurately modeled in most cases as simple resistive capacitive circuits Charging discharging rate proportional to R X C Circuit timing is part of the larger hierarchy of design decisions regarding performance Lecture 04 Timing 2 CS250 UC Berkeley Fall 09 Performance Design Decisions Abstraction Layer Example Choices functional specification algorithm or ISA layout function unit multiplexing pipelining logic organization factoring transistor sizing signal buffering wire lengths layer assignment device wire engineering materials processing microarchitecture RTL transistor circuits Ultimate goal is to meet performance cost area power target for the functional specification Subgoal is meet a upper bound on clock period Lecture 04 Timing CS250 UC Berkeley Fall 09 3 Synchronous Design Clock Constraint 2 Delay in State Elements 1 Delay in Combinational Logic 3 Delay in wires grouped with CL or State 4 Clock Skew T clk Q CL setup clk skew For all paths Today focus on transistor circuit and layout level Microarchitecture RTL later device wire engineering out of our control Lecture 04 Timing 4 CS250 UC Berkeley Fall 09 Parasitics Lecture 01 Introduction 1 5 CS250 UC Berkeley Fall 09 Resistance Lecture 01 Introduction 1 6 CS250 UC Berkeley Fall 09 Resistance Values 45nm process inner metal layers 0 09 Ohms sq outer metal layers 0 028 Ohm sq vias 0 9 Ohm Lecture 01 Introduction 1 7 CS250 UC Berkeley Fall 09 Transistor Resistor Approximation Lecture 01 Introduction 1 8 CS250 UC Berkeley Fall 09 Resistive Effects Lecture 01 Introduction 1 9 CS250 UC Berkeley Fall 09 Parasitic Capacitance Lecture 01 Introduction 1 10 CS250 UC Berkeley Fall 09 Capacitance bet ween layers Lecture 01 Introduction 1 11 CS250 UC Berkeley Fall 09 Capacitance of Diffusion Regions Lecture 01 Introduction 1 12 CS250 UC Berkeley Fall 09 Transistor source drain regions Lecture 01 Introduction 1 13 CS250 UC Berkeley Fall 09 Typical Capacitance Values Lecture 01 Introduction 1 14 CS250 UC Berkeley Fall 09 Gate Capacitance Calculation In a 45nm process a unit inverter delay is 8 10ps Lecture 01 Introduction 1 15 CS250 UC Berkeley Fall 09 Wire Coupling Capacitance Lecture 01 Introduction 1 16 CS250 UC Berkeley Fall 09 Node Coupling Effect Lecture 01 Introduction 1 17 CS250 UC Berkeley Fall 09 Combining R C Same effect applies to series connections of transistors Lecture 01 Introduction 1 18 CS250 UC Berkeley Fall 09 0 25 um process minimal width wires Lecture 01 Introduction 1 19 Combined R C CS250 UC Berkeley Fall 09 Driving RC lines Lecture 01 Introduction 1 20 CS250 UC Berkeley Fall 09 n1 n0 Lecture 01 Introduction 1 21 Rise Falls times and propagation delay CS250 UC Berkeley Fall 09 Timing Optimization In a 45nm process is 4 5ps Lecture 01 Introduction 1 22 CS250 UC Berkeley Fall 09 Lecture 01 Introduction 1 23 CS250 UC Berkeley Fall 09 Lecture 01 Introduction 1 24 CS250 UC Berkeley Fall 09 Driving Large Capacitive Loads Lecture 01 Introduction 1 25 CS250 UC Berkeley Fall 09 Lecture 01 Introduction 1 26 CS250 UC Berkeley Fall 09 Lecture 01 Introduction 1 27 CS250 UC Berkeley Fall 09 Lecture 01 Introduction 1 28 CS250 UC Berkeley Fall 09 Lecture 01 Introduction 1 CS250 UC Berkeley Fall 09 29 Rebuffer Long Wires v1 v2 R v3 v4 C v1 v2 v3 v4 time Wire Delay 2 1 2 1 2 Rtotal X 1 2 Ctotal 1 4 Rtotal X Ctotal 1 4 R C L2 Wire Delay 1 2 Rtotal X Ctotal 1 2 R C L2 Buffer adds some delay With too many splits buffer delay dominates Lecture 01 Introduction 1 30 CS250 UC Berkeley Fall 09 Layout of Large Transistors Modern designs rules don t allow Lecture 01 Introduction 1 31 CS250 UC Berkeley Fall 09 Layout of Large Transistors Modern designs rules don t allow Lecture 01 Introduction 1 32 CS250 UC Berkeley Fall 09 Layout of Three Stage Buffer Lecture 04 Timing CS250 UC Berkeley Fall 09 Timing Closure Searching for and beating down the critical path IEEE JOURNAL OF SOLID STATE CIRCUITS VOL 36 NO 11 NOVEMBER 2001 Must consider all connected register pairs paths from input to register register to output Don t forget the controller Design tools help in the search Synthesis tools work to meet clock constraint report delays on paths Special static timing analyzers accept a design netlist and report path delays and of course simulators can be used to determine timing performance standby power re low voltage tandby current dvantage of the y bias is used mode All core ource and bulk s cobalt disilicapacitance as rformance and tion and data iteback buffer e two and four hit under miss AM like oper 33 Tools that are expected to do something about the timing behavior such as synthesizers also include provisions for specifying input arrival times relative to the clock and output requirements set up times of next stage Fig 2 Microprocessor pipeline organization shown in Fig 2 where the state boundaries are indicated by gray Features that allow the microarchitecture to achieve high speed are as follows The shifter and ALU reside in separate stages The ARM instruction set allows a shift followed by an ALU operation in a single instruction Previous implementations limited frequency ming ta e ours 00 ding ks as plift alysis The critical path Late mode timing checks thousands ets ainst n late n ng Timing Analysis real example Most paths have hundreds of picoseconds to spare 200 150 100 50 0 40 20 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 Timing slack ps From The circuit and physical design of the POWER4 microprocessor IBM J Res and Dev 46 1 Jan 2002 J D Warnock et al Figure 26 Histogram of the POWER4 processor path delays Timing Analysis Tools well as building and initializing the internal data structures the timing The Tools actual Timingmodel Analysis usestatic delaytiming modelsanalysis for forStatic typically tookinterconnect 2 5 3 hours Traces Generation of the entire gates and through circuit paths complement of reports captureand analysis required an additional Delay models 5 to 6 hours to complete total of 1 9delay GB output of timing For each input outputA pair internal load reportsindependent and analysis were generated from each chip timing delay output delaydown analyzed and