Chisel TutorialJonathan Bachrach, Krste Asanovi´c, John WawrzynekEECS Department, UC Berkeley{jrb|krste|johnw}@eecs.berkeley.eduNovember 19, 20111 IntroductionThis document is a tutorial introduction to Chisel (Constructing Hardware In a Scala Embedded Language).Chisel is a hardware construction language embedded in the high-level programming language Scala. Atsome point we will provide a proper reference manual, in addition to more tutorial examples. In the mean-time, this document along with a lot of trial and error should set you on your way to using Chisel. Chisel isreally only a set of special class definitions, predefined objects, and usage conventions within Scala, so whenyou write a Chisel program you are actually writing a Scala program. However, for the tutorial we don’tpresume that you understand how to program in Scala. We will point out necessary Scala features throughthe Chisel examples we give, and significant hardware designs can be completed using only the materialcontained herein. But as you gain experience and want to make your code simpler or more reusable, youwill find it important to leverage the underlying power of the Scala language. We recommend you consultone of the excellent Scala books to become more expert in Scala programming.Chisel is still in its infancy and you are likely to encounter some implementation bugs, and perhaps evena few conceptual design problems. However, we are actively fixing and improving the language, and areopen to bug reports and suggestions. Even in its early state, we hope Chisel will help designers be moreproductive in building designs that are easy to reuse and maintain.Through the tutorial, we format commentary on our design choices as in this paragraph. You should be able to skipthe commentary sections and still fully understand how to use Chisel, but we hope you’ll find them interesting.We were motivated to develop a new hardware language by years of struggle with existing hardware descriptionlanguages in our research projects and hardware design courses. Verilog and VHDL were developed as hardwaresimulation languages, and only later did they become a basis for hardware synthesis. Much of the semantics ofthese languages are not appropriate for hardware synthesis and, in fact, many constructs are simply not synthesiz-able. Other constructs are non-intuitive in how they map to hardware implementations, or their use can accidentlylead to highly inefficient hardware structures. While it is possible to use a subset of these languages and yield accept-able results, they nonetheless present a cluttered and confusing specification model, particularly in an instructionalsetting.However, our strongest motivation for developing a new hardware language is our desire to change the waythat electronic system design takes place. We believe that it is important to not only teach students how to designcircuits, but also to teach them how to design circuit generators—programs that automatically generate designsfrom a high-level set of design parameters and constraints. Through circuit generators, we hope to leverage thehard work of design experts and raise the level of design abstraction for everyone. To express flexible and scalablecircuit construction, circuit generators must employ sophisticated programming techniques to make decisions con-cering how to best customize their output circuits according to high-level parameter values and constraints. WhileVerilog and VHDL include some primitive constructs for programmatic circuit generation, they lack the powerfulfacilities present in modern programming languages, such as object-oriented programming, type inference, supportfor functional programming, and reflection.Instead of building a new hardware design language from scratch, we chose to embed hardware constructionprimitives within an existing language. We picked Scala not only because it includes the programming features wefeel are important for building circuit generators, but because it was specifically developed as a base for domain-specificlanguages.12 Hardware expressible in ChiselThe initial version of Chisel only supports the expression of synchronous RTL (Register-Transfer Level)designs, with a single common clock. Synchronous RTL circuits can be expressed as a hierarchical compo-sition of modules containing combinational logic and clocked state elements. Although Chisel assumes asingle global clock, local clock gating logic is automatically generated for every state element in the designto save power.Modern hardware designs often include multiple islands of logic, where each island uses a different clock and whereislands must correctly communicate across clock island boundaries. Although clock-crossing synchronization circuitsare notoriously difficult to design, there are known good solutions for most scenarios, which can be packaged aslibrary elements for use by designers. As a result, most effort in new designs is spent in developing and verifying thefunctionality within each synchronous island rather than on passing values between islands.In its current form, Chisel can be used to describe each of the synchronous islands individually. Existing toolframeworks can tie together these islands into a complete design. For example, a separate outer simulation frameworkcan be used to model the assembly of islands running together. It should be noted that exhaustive dynamic verificationof asynchronous communications is usually impossible and that more formal static approaches are usually necessary.This version of Chisel also only supports binary logic, and does not support tri-state signals.We focus on binary logic designs as they constitute the vast majority of designs in practice. We omit support fortri-state logic in the current Chisel language as this is in any case poorly supported by industry flows, and difficultto use reliably outside of controlled hard macros.3 Datatypes in ChiselChisel datatypes are used to specify the type of values held in state elements or flowing on wires. Whilehardware designs ultimately operate on vectors of binary digits, other more abstract representations forvalues allow clearer specifications and help the tools generate more optimal circuits. In Chisel, a raw col-lection of bits is represented by the Bits type. Signed and unsigned integers are considered subsets offixed-point numbers and are represented by types Fix and UFix respectively. Signed fixed-point numbers,including integers, are