Simulating Verilog RTL using Synopsys VCSCS250 Tutorial 4 (Version 091209a)September 12, 2010Yunsup LeeIn this tutorial you will gain experience using Synopsys VCS to compile cycle-accurate executablesimulators from Verilog RTL. You will also learn how to use the Synopsys Waveform viewer totrace the various signals in your design. Figure 1 illustrates the basic VCS toolflow and RISC-Vtoolchain. For more information about the RISC-V toolchain consult Tutorial 3: Build, Run, andWrite RISC-V Programs.VCS takes a set of Verilog files as input and produces a simulator. When you execute the simulatoryou need some way to observe your design so that you can measure its performance and verify that itis working correctly. There are two primary ways to observe your design: (1) you can use $displaystatements in your Verilog RTL to output textual trace information, or (2) you can instruct thesimulator to automatically write transition information about each signal in your design to a file.There is standard text format for this type of signal transition trace information called the ValueChange Dump format (VCD). Unfortunately, these textual trace files can become very large veryquickly, so Synopsys uses a proprietary compressed binary trace format called VCD Plus (VPD).You can view VPD files using the Synopsys waveform viewer called Discovery Visual Environment(DVE).VerilogSource(RTL)VCSRTLSimExecute SIMVPDTestOutputsDVE GUIASMSourceCodeRISC-VBinaryRISC-V toolchainCSourceCodeVerilogLibrary(RTL)Figure 1: VCS Toolflow and RISC-V Assembler ToolchainCS250 Tutorial 4 (Version 091209a), Fall 2010 2You will be using a simple unpipelined RISC-V v1 processor as your design example for this tutorial,and thus you will also learn how to build and run test codes on the processor simulator. Figure 2shows the block diagram for the example processor. Figure 1 shows the RISC-V toolchain whichstarts with an RISC-V assembly file and generates a binary file suitable to run on the cycle-accuratesimulator. This tutorial assumes you are familiar with the RISC-V ISA. For more information pleaseconsult the RISC-V Processor Specification.+4Instruction MemRegFileSignExtendDecoder>>1CmpData Memir[24:20]branchpc+4pc_selrd0rd1AddControlSignalseq?wb_selRegFileir[24:20]rf_wenvalrwPCtohosttestrig_tohosttohost_envalop0op1addrwdatardatair[19:15]ir[11:0]Figure 2: Block diagram for Unpipelined RISC-V v1 ProcessorThe following documentation is located in the course locker ~cs250/manuals and provides addi-tional information about VCS, DVE, and Verilog.• vcs-user-guide.pdf - VCS User Guide• vcs-quick-reference.pdf - VCS Quick Reference• vcs dve-user-guide.pdf - Discovery Visual Environment User Guide• vcs ucli-user-guide.pdf - Unified Command Line Interface User Guide• ieee-std-1364-1995-verilog.pdf - Language specification for the original Verilog-1995• ieee-std-1364-2001-verilog.pdf - Language specification for Verilog-2001• ieee-std-1364-2005-verilog.pdf - Language specification for Verilog-2005• ieee-std-1364.1-2002-verilog-synthesis.pdf - Standard for Verilog Register TransferLevel Synthesis• ieee-std-1800-2005-sysverilog.pdf - Language specification for the original SystemVerilog-2005• ieee-std-1800-2009-sysverilog.pdf - Language specification for SystemVerilog-2009CS250 Tutorial 4 (Version 091209a), Fall 2010 3Getting startedYou can follow along through the tutorial yourself by typing in the commands marked with a ’%’symbol at the shell prompt. To cut and paste commands from this tutorial into your bash shell(and make sure bash ignores the ’%’ character) just use an alias to ”undefine” the ’%’ characterlike this:% alias %=""All of the CS250 tutorials should be ran on an EECS Instructional machine. Please see the coursewebsite for more information on the computing resources available for CS250 students. Once youhave logged into an EECS Instructional you will need to setup the CS250 toolflow with the followingcommands.% source ~cs250/tools/cs250.bashrcFor this tutorial you will be using an unpipelined RISC-V v1 processor as your example RTL design.Create a working directory and copy files from the course locker using the following commands.% mkdir tut4% cd tut4% TUTROOT=$PWD% cp -R ~cs250/examples/v-riscv-v1-1stage/* $TUTROOTBefore starting, take a look at the subdirectories in the project directory. All of your projects willhave a similar structure. Source RTL should be placed in the src directory and test input filesshould be placed in the riscv-tests directory. The build directory will contain all generatedcontent including simulators, synthesized gate-level Verilog, and final layout. In this course youwill always try to keep generated content separate from your source RTL. This keeps your projectdirectories well organized, and helps prevent you from unintentionally modifying your source RTL.There are subdirectories in the build directory for each major step in the CS250 toolflow. Thesesubdirectories will contain scripts and configuration files necessary for running the tools requiredfor that step in the toolflow. For example, the build/vcs-sim-rtl directory contains a makefilewhich can build Verilog simulators and run tests on these simulators. For more information, pleaseconsult Tutorial 2: Bits and Pieces of CS250’s toolflow. You should browse the source code for theprocessor in src to become familiar with the design. The csrc directory contains Direct C sourcefiles. These C source files are used in the Verilog test harness to simulate memory, parse and loadELF files. Direct C is a very convenient way to glue Verilog simulation with C functions, whichwill be used through out the course. Please refer to the VCS user guide chapter 19 (C LanguageInterface) for more information on Direct C.Compiling the SimulatorIn this section you will first see how to run VCS from the command line, and then you will see howto automate the process using a makefile. To build the simulator you need to run the vcs compilerwith the appropriate command line arguments and a list of input Verilog files.CS250 Tutorial 4 (Version 091209a), Fall 2010 4% cd $TUTROOT/build/vcs-sim-rtl% vcs -full64 -PP +lint=all,noVCDE +v2k -timescale=1ns/10ps \+vc+list -CC "-I$VCS_HOME/include" \+define+CLOCK_PERIOD=1.25 \+define+IMEM_DELAY=0.4 \+define+DMEM_DELAY=0.4 \../../src/defCommon.vh \../../src/riscvInst.vh \../../src/riscvConst.vh \../../src/riscvProcCtrl.v \../../src/riscvProcDpathRegfile.v \../../src/riscvProcDpath.v