GCD: VLSI’s Hello WorldCS250 Laboratory 1 (Version 091111)Written by Yunsup Lee (2010)Updated by Brian Zimmer (2011)OverviewFor this assignment, you will become familiar with the VLSI tools you will use throughout thissemester, learn how a design “flows” through the toolflow, and practice Chisel coding. Specifically,you will write an RTL model of a greatest common divisor (GCD) circuit, synthesize and place androute the design, simulate at every stage, and analyze power.DeliverablesThis lab is due Monday, September 19th at 1pm. Deliverables for this lab are:• (a) your working Chisel RTL checked into a control system called Git• (b) build results and reports generated by VCS, DC Compiler, Formality, IC Compiler, Prime-Time PX checked into Git• (c) written answers to the questions given at the end of this document checked into git aswriteup/report.pdf or writeup/report.txtYou are encouraged to discuss your design with others in the class, but you must turn in your ownwork.VLSI Toolflow IntroductionFigure 1 shows the toolflow you will be using for the first lab. You will use Synopsys VCS (vcs) tosimulate and debug your RTL design. After you get your design right, you will use Synopsys DesignCompiler (dc shell-xg-t) to synthesize the design. Synthesis is the process of transforming anRTL model into a gate-level netlist. You will use Synopsys Formality (fm shell) to formally verifythat the RTL model and the gate-level model match. VCS is used again to simulate the synthesizedgate-level netlist. After obtaining a working gate-level netlist, you will use Synopsys IC Compiler(icc shell) to place and route the design. Placement is the process by which each standard cell ispositioned on the chip, while routing involves wiring the cells together using various metal layers.The tools will provide feedback on the performance and area of your design after both synthesisand place and route. The results from place and route are more realistic but require much moretime to generate. After place and route, you will generate and simulate the final gate-level netlistusing VCS. Finally you will use this gate-level simulation as a final test for correctness and togenerate transition counts for every net in the design. Synopsys PrimeTime PX (pt shell) takesthese transition counts as input and correlate them with the capacitance values in the final layout toproduce estimated power measurements. The diagram below shows how every tools works together.CS250 Lab Assignment 1 (Version 091111), Fall 2011 2Execute SIMVerilogSource(Behav)BehavSimVCSVPDTestOutputsDVE GUIVerilogSource(RTL)VCS Design CompilerFormalityDesign Vision GUIIC Compiler (DP)IC Compiler (P&R)ConstraintsFileVerificationResultsConstraintsStd.CellLibraryRTLSimGateLevelNetlistTimingAreaDelayFileTLU+FilesFloorPlanConstraintsFileGateLevelNetlistTimingAreaLayoutParasiticsFileDelayFileExecute SIMGuidanceFileVPDTestOutputsDVE GUIVCSPostSynSimExecute SIMVPDTestOutputsDVE GUIVCSPostP&RSimExecute SIMVPDTestOutputsDVE GUIIC Compiler GUIPrimeTimeVCDVPD2VCDPowerEstimatesFigure 1: CS250 Toolflow for Lab 1CS250 Lab Assignment 1 (Version 091111), Fall 2011 3PrerequisitesAs you can easy tell from the diagram, many different tools are needed to take even a simple designfrom RTL all the way to transistor-level implementation. Each tool is immensely complicated, andmany engineers in industry specialize in only one. In order to produce a VLSI design in a singlesemester we will need to understand a little about every one.Each tool has a GUI interface. However, most inputs that the tools need are the same for everydesign iteration and become repetitive to type, so .tcl scripts provide all of the inputs needed. Whenyou use the GUI, in the terminal window you will see the textual equivalent of each click, and thesecommands can be added to scripts. To keep files organized, each piece of the toolflow has its ownbuild directory and its own Makefile. The Makefile initializes the program and points at the setupscripts. A top-level Makefile runs each program in succession so that ideally, a single command willpush an RTL design all of the way through the flow without any repetitive intervention. This willalso allow for easy design space exploration (eg. tweak a variable and see how energy, area, andperformance change).Tutorials have been written to provide more in-depth information than this lab. It is highlyrecommended that you skim these tutorials before beginning the lab, revisit the tutorials in moredepth after you have completed that lab, and revist them again later in the quarter once the processbegins to make more sense. These tutorials work best as companions to the labs.• Tutorial 1: Using Git to Manage Source RTL• Tutorial 2: Bits and Pieces of CS250’s Toolflow• Tutorial 4: Simulating Verilog RTL using Synopsys VCS• Tutorial 5: RTL-to-Gates Synthesis using Synopsys Design Compiler• Tutorial 6: Automatic Placement and Routing using Synopsys IC Compiler• Tutorial 7: Power Analysis using Synopsys PrimeTime PXCS250 Lab Assignment 1 (Version 091111), Fall 2011 4Getting StartedYou can follow along through the lab yourself by typing in the commands marked with a ’%’ symbolat the shell prompt. To cut and paste commands from this lab into your bash shell (and make surebash ignores the ’%’ character) just use an alias to ”undefine” the ’%’ character like this:% alias %=""Note: OS X Preview will not copy newlines correctly, so use Adobe Reader.All of the CS250 laboratory assignments should be completed on an EECS Instructional machine.Please see the course website and follow all of the instructions for setting up your computingresources. Remember, you will need to source a setup script in order for these instructions to work.This bash script contains the location of each tool’s binary, and also sets up important environmentvariables. Please follow the setup instructions on the course website before attempting this lab.You will be using Git to manage your CS250 laboratory assignments. Please see Tutorial 1: UsingGit to Manage Source RTL for more information on how to use Git. Every student has their owndirectory in the repository which is not accessible to other students. The remote repository ishosted on github.com. In order for these instructions to work, you must have told your GSI whatyour github.com username is.We have a template repository which contains all of the files that we provide for your lab. You willclone this