ASIC Implementation of a RISC-V Corewith On-Chip CachesCS250 Laboratory 3 (Version 082511)Written by Yunsup Lee (2010)Updated by Brian Zimmer (2011)OverviewIn the second lab assignment, you wrote an RTL model of a two-stage pipelined RISC-V processorusing Chisel and synthesized your RTL model. In the third lab assignment, you will substitutemagic memory with on-chip caches, extend your design to a full five stage pipeline, and will useall the tools you have learned so far to simulate, synthesize, place and route your design andfinally analyze energy consumption. After producing a preliminary ASIC implementation, you willattempt to optimize your design to make it more energy efficient while meeting your time constraint.The objective of this lab is to introduce memory blocks that you might use in your final project, aswell as to give you some intuition into how high-level hardware descriptions are transformed intolayout.We have provided a 16 KB instruction cache and a 16 KB data cache to use. Both caches have a32-bit wide CPU access port and a 128-bit wide memory refill port. These caches block on a cachemiss. Cache lines are 64 bytes, and both caches are initially set to be a 8-way set associative cache.If you do the math, you should be able to figure out that there are 32 sets. These numbers can bechanged, since the cache is parameterizable.After producing a working RTL model for the core, you will attempt to optimize your design toincrease energy efficiency.DeliverablesThis lab is due Monday, October 24th at 1pm. Deliverables for this lab are:• (a) your optimized Chisel source and all of the scripts necessary to completely generate yourASIC implementation and analyze energy consumption checked into Git• (b) an analytic energy model for your core implementation• (c) written answers to the questions given at the end of this document checked into git aswriteup/report.pdf or writeup/report.txtBefore starting this lab, it is recommended that you revisit the Chisel model you wrote in thesecond lab. Take some time to clean up your code, add comments, and enforce a consistent namingscheme. You will find as you work through this lab assignment that having a more extensive modulehierarchy can be very advantageous; initially we will be preserving module boundaries throughoutthe toolflow which means that you will be able to obtain performance and power results for eachmodule. It will be much more difficult to gain any intuition about the performance or power ofa specific assign statement or always block within a module. Thus you might want to considerCS250 Lab Assignment 3 (Version 082511), Fall 2011 2breaking your design into smaller pieces. For example, if your entire ALU datapath is in onemodule, you might want to create separate submodules for the adder/subtracter unit, shifter unit,and the logic unit. Unfortunately, preserving the module hierarchy throughout the toolflow meansthat the VLSI tools will not be able to optimize across module boundaries. If you are concernedabout this you can explicitly instruct the VLSI tools to flatten a portion of the module hierarchyduring the synthesis process. Flattening during synthesis is a much better approach than lumpinglarge amounts of Verilog into a single module yourself.Block Diagram and Module InterfacesFigure 1 shows the overall diagram. The core module contains the processor, instruction cache,data cache, and an arbiter. The processor is connected to the instruction cache and the data cachewith a similar interface used in the second lab. These interfaces are 32-bits wide. Notice thatthere is a ready signal on the request side, and a valid signal on the response side. This is a morerealistic memory interface, where you might not be able to issue a memory request every cyclebecause the cache is blocked on a miss (when the ready signal on the request side is deasserted), ornot be able to read from memory every cycle because you missed in a cache (when the valid signalon the response side is deasserted). Also notice that the instruction memory refill port and thedata memory refill port needs to arbitrate on the memory refill port going out of the core. Thereare several arbitration policies you can implement, but in this lab you will use a fixed priorityarbitration scheme, where the instruction memory refill port always gets priority over the datamemory refill port. The refill port is 128-bits wide. There will be four transactions on the memoryrefill interface when a cache line transfer occurs, since the cache line size is 64 bytes.For this lab, the instruction and data caches operation is modeled by a C model. You are notresponsible for implementing the caches in Cacti. Your Cacti code is responsible for describing theprocessor core and memory, and all signals to and from the caches are sent out of the top level.For your emulator implementation, these cache signals are hooked up to a functional cache modelfrom emulator.cpp.For your VLSI implementation, there are additional models that describe the timing, area, andpower of these caches as well as functionality. These are generated from a modeling programknown as Cacti.Both caches have a request/response port to/from the processor and a memory refill port. Noticethat the instruction cache interface is simpler compared to the data cache interface since it is aread-only memory. You can take a look at ICache 32x4096 BC.v and DCache 32x4096 BC.v formore details.CS250 Lab Assignment 3 (Version 082511), Fall 2011 3 riscvCore riscvTestHarnessCpufromimem.req_addrimem.req_rdytoclkresetInstructionCache (C model)DataCache (C model)imem.resp_bitsdmem.req_rwdmem.req_addrdmem.req_datadmem.resp_valdmem.resp_datalog_controlimem.req_valimem.resp_valdmem.req_rdydmem.req_valclkreseticache.req_addricache.req_rdyicache.resp_dataicache.req_valicache.resp_valdcache.req_rwdcache.req_addrdache.req_datadcache.resp_valdcache.resp_datadcache.req_rdydcache.req_valArbitermem.req_rwmem.req_addrmem.req_datamem.resp_valmem.resp_datamem.req_rdymem.req_valclkresetmem.req_tagmem.resp_tagclkreset_ext323232128128128128128clkresetio.imemio.dmemio.hostio.dcacheio.icacheio.memFigure 1: Block diagram for RISC-V v2 Core Test HarnessCS250 Lab Assignment 3 (Version 082511), Fall 2011 4The arbiter sees both memory refill requests coming from the instruction cache and the data cacheand puts its decision on the request ready signals. We have provided you with a simple arbiter.Test HarnessWe are providing a test harness to