CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 1CS250VLSI Systems DesignLecture 2: IntroductionFall 2011Krste Asanovic’, John WawrzynekwithJohn LazzaroandBrian Zimmer (TA)CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 1So what has changed in 30 years?2CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 13CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 1Moore’s Law Growth and Effects4CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 188Processed Wafer CostProcessed Wafer CostWafer size conversions offset trend ofWafer size conversions offset trend ofincreasing wafer processing costincreasing wafer processing costSource: IntelSource: IntelSecondary driver: Wafer sizeFrom: “Facing the Hot Chips Challenge Again”, Bill Holt, Intel, presented at Hot Chips 17, 2005.5CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 1Processing advances4µm45nm6CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 1IC Technology Stuff (1)‣Feature size:then: ~4µm now: .032µm moving to: .028µm‣Interconnect:then: 2 layers now: ~10 layers, then: aluminum now: copper‣Transistors:then: planar MOSFET now: same‣Layout and GDRs:Essentially unchanged. More complex. Density and area-fill rules.‣Circuits:then: clocked static CMOS now: same (lots of crazy stuff in between)Interesting, though, most CMOS circuits and layouts designed in 1980 would work if fabricated on today’s IC process.7CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 1IC Technology Stuff (2)‣Transistors:then: near perfect switch now: leaky‣Power consumption:then: dynamic (switching) energy now: approaching 50% static leakage (back to the future - nMOS has similar problem)‣New improved devices coming soon: FinFETs‣Chip Input/Outputthen: parameter pads now: often area pads‣Lithographic Mask Costs:then: few $k now: $M (full die, 65, 45, 28nm)8CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 1IC Technology Stuff (3)‣Device reliability:then: devices nearly never fail future (<65nm): high soft and hard error rates ‣Process variations across die, die-to-die:‣Statistical variations in processing (wire widths/resitivity, transistor dimensions/strengths, doping inconsistencies) become apparent at smaller geometries. ‣Some circuits fast, others slow. Some high-power, some low.‣Yield on leading edge processes dropping dramatically‣IBM quotes yields of 10 – 20% on Cell processor 9CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 1Design Stuff ‣Chip functionality:then: limited by area now: usually limited by energy dissipation‣Design cost:now: design costs in $50M range for full-die custom designs (high percentage in verification)‣Implementation Alternatives: more alternatives that trade up-front design costs for per unit costs.‣FPGA compete aggressively with custom silicon then: most custom designs implemented at silicon level now: many more custom designs implemented with FPGAs‣Standard design abstraction:then: transistors circuits now: RTL in HDLs, standard “cores” and standard cells (higher productivity, somewhat less area/energy efficient) - 10CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 111Implementation AlternativesWhataretheimportantmetricsofcomparison?Full-custom:All circuits/transistors layouts optimized for application.Standard-cell:Arrays of small function blocks (gates, FFs) automatically placed and routed.Gate-array (structured ASIC):Partially prefabricated wafers customized with metal layers or vias.FPGA:Prefabricated chips customized with loadable latches or fuses.Microprocessor:Instruction set interpreter customized through software.Domain Specific Processor:Special instruction set interpreters (ex: DSP, NP, GPU).By “ASIC”, most people mean “Standard-cell” based implementation.CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 112The Important Distinction• Instruction Binding Time‣When do we decide what operation needs to be performed?• General PrinciplesEarlier the decision is bound, the less area, delay/energy required for the implementation.Later the decision is bound, the more flexible the device.A. DeHonCS250, UC Berkeley Fall ‘11Lecture 02, Introduction 113Full-Custom‣Circuit styles and transistors sizes are customized to optimize die, size, power, performance.‣High NRE (non-recurring engineering) costs‣Time-consuming and error prone layout‣Optimizing for small die can result in low per unit costs, extreme-low-power, or extreme-high-performance.‣Common for analog design.‣Requires full set of custom masks.‣High NRE usually restricts use to high-volume applications/markets or highly-constrained and cost insensitive markets.CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 114Standard-Cell*‣Based around a set of pre-designed (and verified) cells‣Ex: NANDs, NORs, Flip-Flops, buffers, …‣Each cell comes complete with:‣ layout (perhaps for different technology nodes and processes),‣Behavioral simulation, delay, & power models.‣Chip layout is automatic, reducing NREs (usually no hand-layout).‣Requires full set of masks - nothing prefabricated.‣Non-optimal use of area and power, leading to higher per die costs than full-custom.‣Commonly used with other design implementation strategies (large blocks for memory, I/O blocks, etc.)CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 115Gate Array‣Store prefabricated wafers of “active” & gate layers & local interconnect, comprising, primarily, rows of transistors. Customize as needed with “back-end” metal processing (contact cuts, vias, metal wires). Could use a different factory.CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 116Gate Array• Shifts large portion of design and mask NRE to vendor.• Shorter design and processing times, reduced time to market.• Highly structured layout with fixed size transistors leads to large sub-circuits (ex: Flip-flops) and higher per die costs.• Memory arrays are particularly inefficient, so often prefabricated, also:Sea-of-gates, structured ASIC, master-slice.CS250, UC Berkeley Fall ‘11Lecture 02, Introduction 117Field Programmable Gate Arrays‣Fuses, EPROM, or Static RAM cells are used to store the “configuration”. ‣Here, it determines function implemented by LUT, selection of Flip-flop, and interconnection points.‣Many FPGAs include special circuits to accelerate adder carry-chain and many special cores: RAMs, MAC, Enet, PCI,