Write and Synthesize a Two-Stage/Three-StageRISC-V v2 ProcessorCS250 Laboratory 2 (Version 092010a)September 20, 2010Yunsup LeeFor the second lab assignment, you are to write an RTL model of a two-stage and a three-stagepipelined RISC-V v2 processor using Verilog and to synthesize your RTL model. After producinga working RTL model, you will attempt to optimize your design to increase performance and/ordecrease area. The deliverables for this lab are (a) your optimized Verilog source and all of thescripts necessary to completely synthesize your RTL implementation checked into SVN, (b) oneassembly test program and one C benchmark program to test your implementation, and (c) writtenanswers to the critical questions given at the end of this document. The lab assignment is due atthe start of class on Monday, October 4. You must submit your written answers electronicallyby adding a directory titled writeup to your lab project directory (lab2/writeup). Electronicsubmissions must be in plain text or PDF format.You are encouraged to discuss your design with others in the class, but you must turn in your ownwork. The two-stage pipeline should perform instruction fetch in the first stage, while the secondpipeline stage should do everything else including data memory access. The three-stage pipelineshould perform pretty similar to the two-stage pipeline, but the ALU operation, data memoryaccess, and the branch evaluation should be done in the third stage. Since the register access isdone in the second stage, bypass muxes are required to support back to back operations in a three-stage pipeline. Since RISC-V does not have a branch delay slot, you will need to handle branchescarefully to ensure that incorrect instructions are not accidental executed.If you need to refresh your memory about pipelining and the MIPS instruction set, we recommendComputer Organization and Design: The Hardware/Software Interface, Fourth Edition, by Pat-terson and Hennessey. More detailed information about the RISC-V architecture can be found inthe RISC-V Processor Specification. For more information about using Synopsys VCS for Verilogsimulation consult Tutorial 4: Simulating Verilog RTL using Synopsys VCS. To learn more aboutSynopsys Design Compiler for synthesis please refer to Tutorial 5: RTL-to-Gates Synthesis usingSynopsys Design Compiler. Detailed information about building, running, and writing RISC-Vassembly and C codes could be found in Tutorial 3: Build, Run, and Write RISC-V Programs.For this assignment, you should focus on writing clean synthesizable code that follows the codingguidelines discussed in section. In particular, place most of your logic in leaf modules and usestructural Verilog to connect the leaf modules in a hierarchy. Avoid tricky hardware optimizations atthis stage, but make sure to separate out datapath and memory components from control circuitry.The system diagram in Figure 4 can be used as an initial template for your two-stage RISC-Vprocessor implementation, but please treat it as a suggestion. Your objective in this lab is toimplement the RISC-V v2 ISA, not to implement the system diagram so feel free to add newcontrol signals, merge modules, or make any other modifications to the system.CS250 Lab Assignment 2 (Version 092010a), Fall 2010 2Processor Interface riscvTestHarnessriscvProctestrig_fromhostimemreq_bits_addrimemreq_valtestrig_tohostclkresetInstructionMemoryDataMemoryimemresp_bits_datadmemreq_rwdmemreq_bits_addrdmemreq_bits_datadmemreq_valdmemresp_bits_dataclkclkFigure 1: Block diagram for RISC-V v2 Processor Test Harnessmodule riscvProc(input clk, reset,input [7:0] testrig_fromhost, // Testrig fromhost portoutput [7:0] testrig_tohost, // Testrig tohost port (must reset to zero)output [31:0] imemreq_bits_addr, // Inst mem port: addr to fetchoutput imemreq_val, // Inst mem port: is imem request valid?input [31:0] imemresp_bits_data, // Inst mem port: returned instructionoutput dmemreq_bits_rw, // Data mem port: read or write (r=0/w=1)output [31:0] dmemreq_bits_addr, // Data mem port: read/write addressoutput [31:0] dmemreq_bits_data, // Data mem port: write dataoutput dmemreq_val, // Data mem port: is dmem request valid?input [31:0] dmemresp_bits_data // Data mem port: returned read data);Figure 2: Interface for RISC-V v2 ProcessorYour processor should be in a module named riscvProc and must have the interface shown inFigure 2. We have provided you with a test harness that will drive the inputs and check theoutputs of your design. The test harness includes the data and instruction memories. We haveprovided separate instruction and data memory ports to simplify the construction of the pipeline,but both ports access the same memory space. The memory ports can only access 32-bit words,and so the lowest two bits of the addresses are ignored (i.e., only imemreq bits addr[31:2]CS250 Lab Assignment 2 (Version 092010a), Fall 2010 3and dmemreq bits addr[31:2] are significant). To make an instruction memory request, setimemreq bits addr to the fetch address and set imemreq val to one. The data will be returnedcombinationally (i.e. there are no clock edges between when a request is made and when the re-sponse returns). To make a data memory request set dmemreq bits rw to zero for a load or one fora store, set dmemreq bits addr to the address, set dmemreq bits data to the store data if needed,and finally set dmemreq val to one. The data will be returned combinationally for loads, while forstores the data will be written at the end of the current clock cycle. Notice that the data write busis a separate unidirectional bus from the data read bus. Bidirectional tri-state buses are usuallyavoided on chip in ASIC designs.Test HarnessWe are providing a test harness to connect to your processor model. The test harness is identicalto the one described in Tutorial 4: Simulating Verilog RTL using Synopsys VCS and Tutorial 5:RTL-to-Gates Synthesis using Synopsys Design Compiler. The test harness loads a RISC-V binaryinto the memory. The provided makefile can load both assembly tests as well as C benchmarksto run on your processor. The test harness will clock the simulation until it sees a non-zero valuecoming back on the testrig tohost register, signifying that your processor has completed a testprogram. The testrig tohost port should be set to zero on reset. A very simple test program isshown in Figure 3.# 0x00000000: Reset vector.addiw $x1, $x0, 1 # Load constant 1 into register x1mtpcr $x1,