GCD: VLSI’s Hello WorldCS250 Laboratory 1 (Version 083010a)August 30, 2010Yunsup LeeFor the first lab assignment, you will write an RTL model of a greatest common divisor (GCD)circuit and push it through all the VLSI tools you will use in the class. The deliverables for this labare (a) your working Verilog RTL checked into a revision control system called Subversion (SVN),(b) build results and reports generated by VCS, DC Compiler, Formality, IC Compiler, PrimeTimePX checked into SVN, and (c) written answers to the questions given at the end of this document.The lab assignment is due at the start of class on Monday, September 13. You must submit yourwritten answers electronically by adding a directory titled writeup to your lab project directory(lab1/trunk/writeup). Electronic submissions must be in plain text or PDF format. You areencouraged to discuss your design with others in the class, but you must turn in your own work.For this assignment, you will become familiar with the VLSI tools you will use this semester, learnhow a design “flows” through the toolflow, and practice Verilog coding.Figure 1 shows the toolflow you will be using for the first lab. You will use Synopsys VCS (vcs) tosimulate and debug your RTL design. After you get your design right, you will use Synopsys DesignCompiler (dc shell-xg-t) to synthesize the design. Synthesis is the process of transforming anRTL model into a gate-level netlist. You will use Synopsys Formality (fm shell) to formally verifythat the RTL model and the gate-level model match. VCS is used again to simulate the synthesizedgate-level netlist. After obtaining a working gate-level netlist, you will use Synopsys IC Compiler(icc shell) to place and route the design. Placement is the process by which each standard cell ispositioned on the chip, while routing involves wiring the cells together using various metal layers.The tools will provide feedback on the performance and area of your design after both synthesisand place and route. The results from place and route are more realistic but require much moretime to generate. After place and route, you will generate and simulate the final gate-level netlistusing VCS. Finally you will use this gate-level simulation as a final test for correctness and togenerate transition counts for every net in the design. Synopsys PrimeTime PX (pt shell) takesthese transition counts as input and correlate them with the capacitance values in the final layoutto produce estimated power measurements.Each piece of the toolflow has its own build directory and its own makefile. Please consult thefollowing tutorials for more information on using the various parts of the toolflow.• Tutorial 2: Bits and Pieces of CS250’s Toolflow• Tutorial 4: Simulating Verilog RTL using Synopsys VCS• Tutorial 5: RTL-to-Gates Synthesis using Synopsys Design Compiler• Tutorial 6: Automatic Placement and Routing using Synopsys IC Compiler• Tutorial 7: Power Analysis using Synopsys PrimeTime PXCS250 Lab Assignment 1 (Version 083010a), Fall 2010 2Execute SIMVerilogSource(Behav)BehavSimVCSVPDTestOutputsDVE GUIVerilogSource(RTL)VCS Design CompilerFormalityDesign Vision GUIIC Compiler (DP)IC Compiler (P&R)ConstraintsFileVerificationResultsConstraintsStd.CellLibraryRTLSimGateLevelNetlistTimingAreaDelayFileTLU+FilesFloorPlanConstraintsFileGateLevelNetlistTimingAreaLayoutParasiticsFileDelayFileExecute SIMGuidanceFileVPDTestOutputsDVE GUIVCSPostSynSimExecute SIMVPDTestOutputsDVE GUIVCSPostP&RSimExecute SIMVPDTestOutputsDVE GUIIC Compiler GUIPrimeTimeVCDVPD2VCDPowerEstimatesFigure 1: CS250 Toolflow for Lab 1CS250 Lab Assignment 1 (Version 083010a), Fall 2010 3Block Diagram and Module InterfaceThe block diagram is shown in Figure 2. Your module should be named as gcdGCDUnit and musthave the interface shown in Figure 3. We have provided you with a test harness that will drive theinputs and check the outputs of your design.gcdGCDUnit gcdTestHarnessoperands_bits_Aoperands_bits_Boperands_valoperands_rdyresult_bits_dataresult_rdyresult_val clkresetFigure 2: Block diagram for GCD Test Harnessmodule gcdGCDUnit#( parameter W = 16 )(input clk, reset,input [W-1:0] operands_bits_A, // Operand Ainput [W-1:0] operands_bits_B, // Operand Binput operands_val, // Are operands valid?output operands_rdy, // ready to take operandsoutput [W-1:0] result_bits_data, // GCDoutput result_val, // Is the result valid?input result_rdy // ready to take the result);Figure 3: Interface for the GCD moduleCS250 Lab Assignment 1 (Version 083010a), Fall 2010 4Getting StartedYou can follow along through the lab yourself by typing in the commands marked with a ’%’ symbolat the shell prompt. To cut and paste commands from this lab into your bash shell (and make surebash ignores the ’%’ character) just use an alias to ”undefine” the ’%’ character like this:% alias %=""All of the CS250 laboratory assignments should be completed on an EECS Instructional machine.Please see the course website for more information on the computing resources available for CS250students. Once you have logged into an EECS Instructional you will need to setup the CS250toolflow with the following commands.% source ~cs250/tools/cs250.bashrcYou will be using SVN to manage your CS250 laboratory assignments. Please see Tutorial 1: UsingSVN to Manage Source RTL for more information on how to use SVN. Every student has theirown directory in the repository which is not accessible to other students. Assuming your usernameis yunsup, you can checkout your personal SVN directory using the following command.% svn checkout $SVNREPO/yunsup vcTo begin the lab you will need to make use of the lab harness located in ~cs250/lab1. The labharness provides makefiles, scripts, and the Verilog test harness required to complete the lab. Thefollowing commands copy the lab harness into your SVN directory and adds the new project toSVN. To simplify the rest of the lab we will also define a ’$LABROOT’ environment variable whichcontains the absolute path to the project’s top-level root directory.% cd vc% mkdir lab1% svn add lab1% cd lab1% mkdir trunk branches tags% cd trunk% cp -R ~cs250/lab1/v-gcd/* .% cd ..% svn add *% svn commit -m "Initial checkin"% svn update% cd trunk% LABROOT=$PWDThe resulting $LABROOT directory contains the following primary subdirectories: src contains yoursource Verilog; build contains automated makefiles and scripts for building your design; andbuild.manual is the