Lecture 9, Memory CS250, UC Berkeley, Fall 2011CS250 VLSI Systems DesignLecture 9: MemoryJohn Wawrzynek, Krste Asanovic,withJohn LazzaroandBrian Zimmer (TA)UC BerkeleyFall 2011CS250, UC Berkeley, Fall 20111Lecture 9, MemoryCMOS BistableCross-coupled inverters used to hold state in CMOS“Static” storage in powered cell, no refresh neededIf a storage node leaks or is pushed slightly away from correct value, non-linear transfer function of high-gain inverter removes noise and recirculates correct valueTo write new state, have to force nodes to opposite state2D D“1” “0”D D“0” “1”Flip StateCS250, UC Berkeley, Fall 20111Lecture 9, MemoryCMOS Transparent LatchLatch transparent (output follows input) when clock is high, holds last value when clock is low3Optional Input BufferOptional Output BufferD QClkClkClkClkDQClkDQClkSchematic SymbolsTransparent on clock lowTransmission gate switch with both pMOS and nMOS passes both ones and zeros wellCS250, UC Berkeley, Fall 20111Lecture 9, MemoryLatch Operation4D Q1100DClock HighLatch TransparentD Q0011QClock LowLatch HoldingCS250, UC Berkeley, Fall 20111Lecture 9, MemoryFlip-Flop as Two Latches5QClkClkClkClkHoldD QClkClkClkClkSampleQDClkClkSchematic SymbolsThis is how standard cell flip-flops are built(usually with extra in/out buffers)CS250, UC Berkeley, Fall 20111Lecture 9, MemorySmall Memories from Stdcell LatchesAdd additional ports by replicating read and write port logic (multiple write ports need mux in front of latch)Expensive to add many ports6Write Address DecoderRead Address DecoderClkWrite AddressWrite DataRead AddressClkCombinational logic for read port (synthesized)Optional read output latchData held in transparent-low latchesWrite by clocking latchCS250, UC Berkeley, Fall 20111Lecture 9, Memory6-Transistor SRAM (Static RAM)7Large on-chip memories built from arrays of static RAM bitcells, where each bit cell holds a bistable (cross-coupled inverters) and two access transistors.Other clocking and access logic factored out into peripheryBit BitWordlineCS250, UC Berkeley, Fall 20111Lecture 9, MemoryIntel’s 22nm SRAM cell8!"#$%&''(&&%)*%!+,-%."/$%012#!"!#$%&'$()%*+,%)'-..,)*%/012%3,..%(4%5678(49%3(73&(*)%7,:67*,;%*6%;-*,0.092 um2SRAM cell for high density applications0.108 um2SRAM cell for low voltage applications[Bohr, Intel, Sept 2009]CS250, UC Berkeley, Fall 20111Lecture 9, MemoryGeneral SRAM Structure9Address Decode and Wordline DriverDifferential Read Sense AmplifiersDifferential Write DriversBitline PrechargersAddressWrite DataRead DataUsually maximum of 128-256 bits per row or columnClkClkWrite EnableCS250, UC Berkeley, Fall 20111Lecture 9, MemoryAddress Decoder Structure10A1A0A3A22:4 PredecodersClocked Word Line EnableAddressWord Line 0Word Line 1Word Line 15Unary 1-of-4 encodingCS250, UC Berkeley, Fall 20111Lecture 9, MemoryRead Cycle111) Precharge bitlines and senseamp1)2) Pulse wordlines, develop bitline differential voltage2)Bitline differentialClkBit/BitWordlineSenseData/Data3) Disconnect bitlines from senseamp, activate sense pulldown, develop full-rail data signals3)Full-rail swingPulses generated by internal self-timed signals, often using “replica” circuits representing critical pathsClkSenseDataDataFrom DecoderWordline ClockPrechargersSense AmpStorage CellsBitBitOutput Set-Reset LatchCS250, UC Berkeley, Fall 20111Lecture 9, MemoryWrite Cycle121) Precharge bitlines1)ClkBit/BitWordline2) Open wordline, pull down one bitline full rail2)ClkWrite DataFrom DecoderWordline ClockPrechargersStorage CellsBitBitWrite EnableWrite-enable can be controlled on a per-bit level. If bit lines not driven during write, cell retains value (looks like a read to the cell).CS250, UC Berkeley, Fall 20111Lecture 9, MemoryColumn-Muxing at Sense Amps13Sel1ClkSel0From DecoderWordline ClockSense AmpDifficult to pitch match sense amp to tight SRAM bit cell spacing so often 2-8 columns share one sense amp. Impacts power dissipation as multiple bitline pairs swing for each bit read.DataDataCS250, UC Berkeley, Fall 20111Lecture 9, MemoryBuilding Larger Memories14Bit cellsDecI/OBit cellsI/OBit cellsDecBit cellsBit cellsDecI/OBit cellsI/OBit cellsDecBit cellsBit cellsDecI/OBit cellsI/OBit cellsDecBit cellsBit cellsDecI/OBit cellsI/OBit cellsDecBit cellsLarge arrays constructed by tiling multiple leaf arrays, sharing decoders and I/O circuitrye.g., sense amp attached to arrays above and belowLeaf array limited in size to 128-256 bits in row/column due to RC delay of wordlines and bitlinesAlso to reduce power by only activating selected sub-bankIn larger memories, delay and energy dominated by I/O wiringCS250, UC Berkeley, Fall 20111Lecture 9, MemoryAdding More Ports15BitA BitAWordlineAWordlineBBitBBitBWordlineRead BitlineDifferential Read or Write portsOptional Single-ended Read portCS250, UC Berkeley, Fall 20111Lecture 9, MemoryMemory CompilersIn ASIC flow, memory compilers used to generate layout for SRAM blocks in designOften hundreds of memory instances in a modern SoCMemory generators can also produce built-in self-test (BIST) logic, to speed manufacturing testing, and redundant rows/columns to improve yieldCompiler can be parameterized by number of words, number of bits per word, desired aspect ratio, number of sub banks, degree of column muxing, etc.Area, delay, and energy consumption complex function of design parameters and generation algorithmWorth experimenting with design spaceUsually only single read or write port SRAM and one read and one write SRAM generators in ASIC library16CS250, UC Berkeley, Fall 20111Lecture 9, MemorySmall Memories17Compiled SRAM arrays usually have a high overhead due to peripheral circuits, BIST, redundancy. Small memories are usually built from latches and/or flip-flops in a stdcell flowCross-over point is usually around 1K bits of storageShould try design both waysCS250, UC Berkeley, Fall 2011Lecture 9, MemoryMemory Design Patterns18CS250, UC Berkeley, Fall 20111Lecture 9, MemoryMultiport Memory Design PatternsOften we require multiple access ports to a common memoryTrue Multiport MemoryAs describe earlier in lecture, completely independent read and write port circuitryBanked Multiport MemoryInterleave lesser-ported banks to provide higher bandwidthStream-Buffered Multiport MemoryUse single wider access port to provide multiple narrower streaming portsCached Multiport MemoryUse large single-port main memory, but add cache to service 19CS250, UC Berkeley, Fall 20111Lecture 9, MemoryTrue